Method and device for testing the mapping/implementation of a model of a logic circuit onto/in a hardware emulator
OwnerHerbert Taucher, Karltheinz Krause +1inventors
InventorsHerbert Taucher, Karltheinz Krause, Majid Ghameshlu
Life of this patent
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Abstract
A method for testing an emulated logic circuit is described wherein a model of the logic circuit is loaded into a hardware emulator (EM) and there put into an operating mode in which flip-flops it contains are functionally chained into one or more shift registers. The structural arrangement of the logic circuit in the hardware emulator (EM) is subsequently compared with the structural arrangement of the model of the logic circuit with the assistance of this operating mode. A device for implementing the method is also described.
Claims9
Method for function testing an emulated logic circuit wherein a model of a logic circuit is loaded into a hardware emulator (EM) in a hardware description language, wherein:
- the emulated logic circuit is put into an operating mode in which some or all of the flip-flops it contains, in particular with additional logic elements as interfacing circuitry, are functionally chained into one or more shift registers, and
- the structural arrangement of the logic circuit in the hardware emulator (EM) is compared with the structural arrangement of the model of the logic circuit at least partially with the assistance of this operating mode.
A Device for testing an emulated logic circuit, comprising:
- a hardware emulator (EM) for emulating a logic circuit present in the form of a model, a test pattern generator module (PC) for applying a test pattern to an input (Ix) of the hardware emulator (EM), a pulse generator for injecting a pulse into the hardware emulator (EM), and a test pattern checking module (PC) for checking whether a bit pattern being applied to an output (Ox) of the hardware emulator (EM) matches an expected value, the device additionally contains a module for comparing the structural arrangement of the logic circuit in the hardware emulator (EM) with the structural arrangement of the model of the logic circuit at least partially with the assistance of an operating mode of the logic circuit in which some or all of the flip-flops it contains, in particular with additional logic elements as interfacing circuitry, are functionally chained into one or more shift registers.
Dependencies are inferred from the claim text.