Microcomputer
AssigneeRenesas Technology Corp.
InventorMasayuki Konishi
Life of this patent
Estimating the term…
Abstract
A CPU of a microcomputer according to the present invention executes a write operation for setting data in a special function register (SFR) while a peripheral enable signal is asserted, and then asserts the peripheral enable signal for one more cycle. By doing so, a peripheral read/write signal becomes effective and the SFR outputs the data set during the write operation onto a peripheral data bus. Therefore, it is possible to check whether the data is successfully written in the SFR within a shorter period of time by automatically executing a read instruction immediately after a write instruction is executed.
Claims9
A microcomputer comprising:
- a central processing unit (CPU) that executes instructions;
- an instruction storage memory that stores the instructions to be executed by the CPU;
- at least one of operation mode setting registers each in which an operation mode for a peripheral module is set;
- and
- a bus interface unit connected to the instruction storage memory by a memory bus, and connected to the operation mode setting registers by a peripheral bus, wherein
- by executing a write operation in accordance with a write instruction to set data in predetermined one of the operation mode setting registers while a peripheral enable signal is asserted, and executing a read operation by asserting the peripheral enable signal for one more cycle after the write operation is executed,
- the CPU outputs the data set through the write operation to a peripheral data bus of the peripheral bus in an instruction fetch period in which a next instruction is read from the instruction storage memory through the bus interface unit.
A microcomputer comprising:
- a central processing unit (CPU) that executes instructions;
- an instruction storage memory that stores the instructions to be executed by the CPU;
- at least one of operation mode setting registers each in which an operation mode for a peripheral module is set;
- a bus interface unit connected to the instruction storage memory by a memory bus, and connected to the operation mode setting registers by a peripheral bus;
- a first test register connected to the bus interface unit by a dedicated data bus;
- and
- a second test register connected to the bus interface unit by a peripheral data bus of the peripheral bus, wherein
- the CPU executes a write operation in accordance with a write instruction to set data in predetermined one of the operation mode setting registers while a peripheral enable signal is asserted, and then outputs a signal for asserting the peripheral enable signal for two more cycles after the write operation is executed,
- during the write operation, the CPU sets identical data in the predetermined operation mode setting register and the first test register, and the first test register sets inverted data of the data set therein in the second test register,
- the second test register outputs the set data onto the peripheral data bus during a read operation in a next cycle to the write operation, and
- the predetermined operation mode setting register outputs the set data onto the peripheral data bus during a read operation in a further next cycle to the write operation.
Dependencies are inferred from the claim text.