Apparatus and method for providing power management on multi-threaded processors
AssigneeIntel Corporation
InventorsBarnes Cooper, Grant H. Kobayashi
Life of this patent
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Abstract
A power management technique uses system management interrupt (SMI) to manage states of a processor that includes multiple logical processors. When the SMI is generated, the states of logical processors are verified. When all of the logical processors are idle, the physical processor is placed in a low power state.
Claims49
A method, comprising:
- using system management mode (SMM) to place a physical processor into a lower power state, the physical processor including multiple logical processors.
A computer readable medium containing executable instructions which, when executed in a processing system, causes the processing system to perform a method comprising:
- enabling a system management interrupt (SMI) trap to verify states of two or more logical processors in a physical processor;
- and
- placing the physical processor into a lower power state when the states of the logical processors are verified to be idle.
A system, comprising:
- a physical processor, the physical processor includes a first logical processor and a second logical processor, wherein the state of the physical processor is managed by generating a system management interrupt (SMI) to verify states of the first logical processor and the second logical processor.
A system, comprising:
- a memory;
- a physical processor coupled to the memory, the physical processor including a first logical processor and a second logical processor, wherein system management mode (SMM) is used to enable placing the physical processor into a low power state.
A method, comprising:
- receiving a first system management interrupt (SMI) associated with a first logical processor;
- determining if both the first logical processor and a second logical processor are idle, the second logical processor coupled to the first logical processor;
- and
- when both the first and the second logical processors are determined to be idle, placing a physical processor into a low power state, the physical processor including the first and second logical processors.
A computer readable medium containing executable instructions which, when executed in a processing system, causes the processing system to perform a method comprising:
- receiving a first system management interrupt (SMI) when a specific instruction is processed by a first logical processor or by a second logical processor at a first time, the second logical processor coupled to the first logical processor;
- determining if both the first logical processor and the second logical processor are idle;
- and
- when both the first and the second logical processors are determined to be idle, placing a physical processor into a low power state, the physical processor including the first and second logical processors.
Dependencies are inferred from the claim text.