Apparatus and method for multi-threaded processors performance control
AssigneeIntel Corporation
InventorsBarnes Cooper, Grant H. Kobayashi
Life of this patent
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Abstract
A power management technique uses system management interrupt (SMI) to manage performance states of logical processors in a physical processor. Each logical processor is associated with a virtual performance state and an actual performance state. A request to retrieve or to change the virtual performance state causes the SMI to be generated. The virtual performance state is a state known to an operating system (OS). The actual performance state is a state that the logical processor is operating at.
Claims30
A method, comprising:
- using system management mode (SMM) to manage performance states of two or more logical processors in a physical processor, wherein each of the two or more logical processor is associated with a virtual performance state and an actual performance state, and wherein the SMM is used to access the virtual performance state and the actual performance state.
A computer readable medium containing executable instructions which, when executed in a processing system, causes the processing system to perform a method comprising:
- using system management interrupt (SMI) to retrieve a virtual performance state of a first logical processor and to change the virtual performance state of the first logical processor, wherein the first logical process is included in a physical processor having two or more logical processors, wherein an actual performance state of the first logical processor may be higher than its virtual performance state.
A method, comprising:
- using system management interrupt (SMI) to retrieve a virtual performance state of a first logical processor and to change the virtual performance state of the first logical processor, wherein the first logical processor is included in a physical processor having two or more logical processors, wherein an actual performance state that the first logical processor is to operate at can be different from its virtual performance state that is known to an operating system (OS).
A system, comprising:
- a physical processor coupled to the memory, the physical processor includes a first logical processor and a second logical processor, wherein performance states of the first logical processor and of the second logical processor are managed by generating a system management interrupt (SMI) and by controlling a virtual performance state register and an actual performance state register associated with each of the logical processors.
Dependencies are inferred from the claim text.