Real time data encryption/decryption system and method for IDE/ATA data transfer

A data ciphering system comprising at least one cryptographic interface operatively coupled between at least one host device and at least one data storage device, and adapted to perform real time data encryption during IDE/ATA data transfer between said at least one host device and said at least one data storage device without affecting the overall data transfer efficiency.

A data ciphering system comprising at least one cryptographic interface operatively coupled between at least one host device and at least one data storage device, and adapted to perform real time data decryption during IDE/ATA data transfer between said at least one host device and said at least one data storage device without affecting the overall data transfer efficiency.

A data ciphering system comprising at least one cryptographic interface operatively coupled between at least one host device and at least one data storage device, said at least one cryptographic interface adapted to intercept at least one IDE/ATA data transfer between said at least one host device and said at least one data storage device, and transparently perform real time data cipher processing on said at least one intercepted IDE/ATA data transfer.

A cryptographic interface for IDE/ATA data transfer intervention, said cryptographic interface comprising:

• a first IDE controller supporting partial ATA protocol,
• a second IDE controller supporting partial ATA protocol, said second IDE controller being operatively coupled to said first IDE controller,
• said first and second IDE controllers being adapted to forward IDE/ATA dataflow control signals between at least one host IDE controller of at least one host device and at least one data storage IDE controller of at least one data storage device while data is streaming between said at least one host device and said at least one data storage device during IDE/ATA data transfer, each of said at least one host IDE controller and said at least one data storage IDE controller supporting full ATA protocol.

A cryptographic interface for IDE/ATA data transfer intervention, said cryptographic interface comprising:

• a first IDE controller supporting partial ATA protocol,
• a second IDE controller supporting partial ATA protocol, said second IDE controller being operatively coupled to said first IDE controller,
• said first and second IDE controllers being adapted to delay forwarding of IDE/ATA dataflow control signals between at least one host IDE controller of at least one host device and at least one data storage IDE controller of at least one data storage device if data is not streaming between said at least one host device and said at least one data storage device during IDE/ATA data transfer, each of said at least one host IDE controller and said at least one data storage IDE controller supporting full ATA protocol.

A cryptographic interface for IDE/ATA data transfer intervention, said cryptographic interface comprising:

• a first IDE controller supporting partial ATA protocol,
• a second IDE controller supporting partial ATA protocol, said second IDE controller being operatively coupled to said first IDE controller,
• said first and second IDE controllers being adapted to forward dataflow control signals between at least one host IDE controller of at least one host device and at least one data storage IDE controller of at least one data storage device while data is streaming between said at least one host device and said at least one data storage device during UDMA/Multi-word DMA data transfer, each of said at least one host IDE controller and said at least one data storage IDE controller supporting full ATA protocol.

A cryptographic interface for IDE/ATA data transfer intervention, said cryptographic interface comprising:

• a first IDE controller supporting partial ATA protocol,
• a second IDE controller supporting partial ATA protocol, said second IDE controller being operatively coupled to said first IDE controller,
• said first and second IDE controllers being adapted to delay forwarding of dataflow control signals between at least one host IDE controller of at least one host device and at least one data storage IDE controller of at least one data storage device if data is not streaming between said at least one host device and said at least one data storage device during UDMA/Multi-word DMA data transfer, each of said at least one host IDE controller and said at least one data storage IDE controller supporting full ATA protocol.

A cryptographic interface for IDE/ATA data transfer intervention, said cryptographic interface comprising:

• a first IDE controller supporting partial ATA protocol,
• a second IDE controller supporting partial ATA protocol, said second IDE controller being operatively coupled to said first IDE controller,
• said first and second IDE controllers being adapted to forward dataflow control signals between at least one host IDE controller of at least one host device and at least one data storage IDE controller of at least one data storage device while data is streaming between said at least one host device and said at least one data storage device during PIO data transfer, each of said at least one host IDE controller and said at least one data storage IDE controller supporting full ATA protocol.

A cryptographic interface for IDE/ATA data transfer intervention, said cryptographic interface comprising:

• a first IDE controller supporting partial ATA protocol,
• a second IDE controller supporting partial ATA protocol, said second IDE controller being operatively coupled to said first IDE controller,
• said first and second IDE controllers being adapted to delay forwarding of dataflow control signals between at least one host IDE controller of at least one host device and at least one data storage IDE controller of at least one data storage device if data is not streaming between said at least one host device and said at least one data storage device during PIO data transfer, each of said at least one host IDE controller and said at least one data storage IDE controller supporting full ATA protocol.