Method and apparatus for fetching instructions from the memory subsystem of a mixed architecture processor into a hardware emulation engine

A method for fetching a line of instructions from a memory subsystem of a mixed architecture CPU into a macroinstruction queue of an emulation engine comprising,

• determining whether the macroinstruction queue is full or will become full with one or more lines of instructions returning from one or more pending fetch requests;
• and
• if the macroinstruction queue is not full and will not become full with one or more lines of instructions returning from one or more pending fetch requests,
• sending a fetch address to a fetch engine;
• retrieving a line of instructions from a memory subsystem into the fetch engine;
• sending the line of instructions to the emulation engine;
• sending a fetch complete signal from the fetch engine to the emulation engine along with the line of instructions;
• if the macroinstruction queue is full or will become full with one or more lines of instructions returning from one or more pending fetch requests, waiting until the macroinstruction queue is not full and will not become full before sending a fetch address to the fetch engine;
• storing the fetch address in a queue of the emulation engine, wherein the queue in the emulation engine mirrors the fetch address queue;
• progressing the fetch address through pipeline stages of the fetch engine and the emulation engine synchronously using pipeline advance logic;
• receiving at the pipeline advance logic a delayed version of the fetch complete signal;
• and
• advancing the fetch address through the fetch engine and the emulation engine based on the delayed version of the fetch complete signal.

A multi-architecture computer system capable of implementing a native instruction set architecture (ISA) and an emulated ISA comprising:

• a memory subsystem of a native ISA;
• a fetch engine of the native ISA, said fetch engine being electrically connected to the memory subsystem of the native ISA wherein the fetch engine accesses the memory subsystem to retrieve a line of instructions from the memory subsystems;
• an engine of an emulated ISA, wherein the engine of the emulated ISA is electrically connected to the fetch engine and interfaces with the fetch engine using a handshake protocol, wherein the engine of the emulated ISA receives a line of instructions and a fetch complete signal from the fetch engine;
• and
• a fetch address queue that stores a fetch address for the line of instructions retrieved from the memory subsystem, wherein the fetch address queue is controlled by the fetch complete signal such that the fetch address is stored in the fetch address queue until the fetch complete signal is received.