Methods and apparatus to support conditional execution in a VLIW-based array processor with subword execution

A hierarchical conditional execution instruction format comprising:

• a plurality of instruction bits defining an instruction;
• a 3-bit, 2-bit or 1-bit subset of said plurality of instruction bits providing an opcode extension encoding for each instruction that supports conditional execution;
• a set of general-purpose arithmetic condition flags (ACFs) that store specified results from instruction execution;
• and
• a set of arithmetic scalar flags (ASFs).

A method of condition generation comprising the steps of:

• defining a set of arithmetic condition flags (ACFs);
• determining side effects of a plurality of scalar conditions on an instruction by instruction basis;
• setting a set of arithmetic scalar flags (ASFs) to save the determined side effects;
• specifying a condition code utilizing a compare instruction;
• and
• updating the ACFs based upon the specified condition code.

A system for generating complex conditions formed by a Boolean combination of relations comprising:

• an arithmetic unit which receives at least two operands from a register file;
• instruction control lines derived from a registered instruction in a processor pipeline, the instruction control lines including conditional execution control lines to control conditional operation as specified in an instruction;
• the arithmetic unit producing a result and a latched arithmetic scalar condition state;
• a first latch for holding the arithmetic scalar condition state for the instruction after the instruction has finished its execution state;
• a second latch connected to the conditional execution control lines for holding instruction control signals for the instruction after the instruction has finished its execution state;
• an arithmetic condition flag (ACF) generation unit for providing a Boolean combination of a present selected state with a previous state;
• and
• an ACF latch for storing the previous state and feeding the previous state back to the ACF generation unit.

A single instruction multiple data stream (SIMD) machine with a controller (SP) and at least two processing elements (PEs), each PE in said SIMD machine comprising:

• an arithmetic unit which receives at least two operands from a register file;
• instruction control lines derived from a registered instruction that was received from the SP in a processor pipeline, the instruction control lines including conditional execution control lines to control conditional operation as specified in an instruction;
• the arithmetic unit producing a result and a latched arithmetic scalar condition state;
• a first latch for holding the arithmetic scalar condition state for the instruction after the instruction has finished its execution state;
• a second latch connected to the conditional execution control lines for holding instruction control signals for the instruction after the instruction has finished its execution state;
• an arithmetic condition flag (ACF) generation unit for providing a Boolean combination of a present selected state with a previous state;
• and
• an ACF latch for storing the previous state and feeding the previous state back to the ACF generation unit.

An indirect very long instruction word (VLIW) processing system comprising:

• a first processing element (PE) having a VLIW instruction memory (VIM) for storing instructions in slots within a VIM memory locations;
• a first register for storing a function instruction having a plurality of group bits defining instruction type and a plurality of unit field bits defining execution unit type;
• a predecoder for decoding the plurality of group bits and the plurality of unit field bits;
• and
• a load mechanism for loading the function instruction in an appropriate one of said slots in VIM based upon said decoding, the first processor further comprising:
• at least two execution units, each execution unit receiving at least two operands from a register file;
• each execution unit having instruction control lines derived from a registered instruction in a processor pipeline, the instruction control lines including conditional execution control lines to control conditional operation as specified in an instruction to be executed;
• each execution unit producing a result and a latched arithmetic scalar condition state;
• each execution unit having a first latch for holding the arithmetic scalar condition state for the instruction after the instruction has finished its execution state;
• each execution unit having a second latch connected to the conditional execution control lines for holding instruction control signals for the instruction after the instruction has finished its execution state;
• each execution unit having an arithmetic condition flag (ACF) generation unit for providing a Boolean combination of a present selected state with a previous state;
• and
• a single ACF latch for all of the execution units for storing the previous state and feeding the previous state back to the respective ACF generation unit.

A system for generating complex conditions comprising:

• an arithmetic unit which receives at least two operands from a register file;
• instruction control lines derived from a registered instruction in a processor pipeline, the instruction control lines including conditional execution control lines to control conditional operation as specified in an instruction;
• the arithmetic unit producing a result and a latched arithmetic scalar condition state;
• a first latch for holding the arithmetic scalar condition state for the instruction after the instruction has finished its execution state;
• a second latch connected to the conditional execution control lines for holding instruction control signals for the instruction after the instruction has finished its execution state;
• an arithmetic condition flag (ACF) generation unit for providing a present selected state of a plurality of arithmetic condition flags (ACFs);
• and
• an ACF latch for storing a previous state for the ACFs and feeding the previous state back to the ACF generation unit.

A single instruction multiple data stream (SIMD) machine with a controller (SP) and at least two processing elements (PEs), each PE in said SIMD machine comprising:

• an arithmetic unit which receives at least two operands from a register file;
• instruction control lines derived from a registered instruction that was received from the SP in a processor pipeline, the instruction control lines including conditional execution control lines to control conditional operation as specified in an instruction;
• the arithmetic unit producing a result and a latched arithmetic scalar condition state;
• a first latch for holding the arithmetic scalar condition state for the instruction after the instruction has finished its execution state;
• a second latch connected to the conditional execution control lines for holding instruction control signals for the instruction after the instruction has finished its execution state;
• an arithmetic condition flag (ACF) generation unit for providing a present selected state of a plurality of arithmetic condition flags (ACFs);
• and
• an ACF latch for storing a previous state for the ACFs and feeding the previous state back to the ACF generation unit.

An indirect very long instruction word (VLIW) processing system comprising:

• a first processing element (PE) having a VLIW instruction memory (VIM) for storing instructions in slots within a VIM memory locations;
• a first register for storing a function instruction having a plurality of group bits defining instruction type and a plurality of unit field bits defining execution unit type;
• a predecoder for decoding the plurality of group bits and the plurality of unit field bits;
• and
• a load mechanism for loading the function instruction in an appropriate one of said slots in VIM based upon said decoding, the first processor further comprising:
• at least two execution units, each execution unit receiving at least two operands from a register file;
• each execution unit having instruction control lines derived from a registered instruction in a processor pipeline, the instruction control lines including conditional execution control lines to control conditional operation as specified in an instruction to be executed;
• each execution unit producing a result and a latched arithmetic scalar condition state;
• each execution unit having a first latch for holding the arithmetic scalar condition state for the instruction after the instruction has finished its execution state;
• each execution unit having a second latch connected to the conditional execution control lines for holding instruction control signals for the instruction after the instruction has finished its execution state;
• each execution unit having an arithmetic condition flag (ACF) generation unit for providing a present selected state of plurality of arithmetic condition flags (ACFs);
• and
• a single ACF latch for all of the execution units for storing a previous state for the ACFs and feeding the previous state back to the respective ACF generation unit.