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AssigneesRicoh Company, Ltd., Ricoh Silicon Valley Corporation
InventorMichael A. Baxter
Estimating the term…
A set of S-machines, a T-machine corresponding to each S-machine, a General Purpose Interconnect Matrix (GPIM), a set of I/O T-machines, a set of I/O devices, and a master time-base unit form a system for scalable, parallel, dynamically reconfigurable computing. Each S-machine is a dynamically reconfigurable computer having a memory, a first local time-base unit, and a Dynamically Reconfigurable Processing Unit (DRPU). The DRPU is implemented using a reprogrammable logic device configured as an Instruction Fetch Unit (IFU), a Data Operate Unit (DOU), and an Address Operate Unit (AOU), each of which are selectively reconfigured during program execution in response to a reconfiguration interrupt or the selection of a reconfiguration directive embedded within a set of program instructions. Each reconfiguration interrupt and each reconfiguration directive references a configuration data set specifying a DRPU hardware organization optimized for the implementation of a particular Instruction Set Architecture (ISA). The IFU directs reconfiguration operations, instruction fetch and decode operations, memory access operations, and issues control signals to the DOU and the AOU to facilitate instruction execution. The DOU performs data computations, and the AOU performs address computations. Each T-machine is a data transfer device having a common interface and control unit, one or more interconnect I/O units, and a second local time-base unit. The GPIM is a scalable interconnect network that facilitates parallel communication between T-machines. The set of T-machines and the GPIM facilitate parallel communication between S-machines. The T-machines also control the transfer of data between S-machines in the network, and provide the addressing operations required. A meta-address is used to provide scalable bit-addressable capability to every S-machine.
A meta-addressing architecture for a network of dynamically reprogrammable processing machines, the meta-address specifying a local memory destination for a data packet comprising:
The addressing machine of claim l, wherein at least one of the addressing machines further comprising:
A method for processing instructions in a parallel processor architecture having local processing machines coupled to local addressing machines and local memory, and the addressing machines are identified by unique geographic identifications and are interconnected through an interconnection unit, comprising the steps of:
The method of claim.6 wherein the addressing machine performs the steps of:
A method for addressing memory in a parallel computing environment in which local processing units are coupled to local memory, local addressing machines, and an interconnect unit, the addressing machine performing the steps of:
A method for processing instructions in a parallel processor architecture having local processing machines coupled to local addressing machines and local memory, and the addressing machines are identified by unique geographic identifications and are interconnected through an interconnection unit, comprising the steps of:
A method for addressing memory in a parallel computing environment in which local processing units are coupled to local memory, local addressing machines, and an interconnect unit, the addressing machine performing the steps of:
Dependencies are inferred from the claim text.