Memory pool configuration system
AssigneeWind River Systems, Inc.
InventorDan Krejsa
Life of this patent
Estimating the term…
Abstract
A memory partitioning system for memory of an embedded or auxiliary processor is described. Memory regions with different attributes are formed, having specified cacheability and visibility characteristics. A configurable table describes the memory regions required by the software running on the auxiliary processor.
Claims18
A memory configuration system for an auxiliary processor having an internal bus and connectable to an external system via at least one external bus, the system comprising:
- a memory configuration table including a plurality of entries, each of the plurality of entries corresponding to one of a plurality of regions of auxiliary processor memory and including at least one location field, at least one size field, and at least one visibility field;
- a module configured to partition the auxiliary processor memory into the plurality of regions, including assigning values to the at least one location field, at least one size field, and at least one visibility field,
- wherein the at least one visibility field includes a field indicating visibility of the corresponding region by at least one of the internal bus and the at least one external bus.
A method of partitioning a memory of an auxiliary processor, comprising:
- constructing a memory configuration table configured to contain size and visibility attributes of a plurality of memory regions, the visibility attributes corresponding to accessibility of each of the plurality of memory regions via at least one bus of a plurality of buses;
- computing a range of memory addresses accessible over the at least one bus for caching the plurality of memory regions;
- and
- setting registers of the auxiliary processor to map memory according to the size, visibility attributes and range of memory addresses for each of the plurality of memory regions.
A computer readable medium having stored thereon instructions adapted to be executed by a processor, wherein the instructions when executed initiate a method for partitioning a memory of an auxiliary processor, comprising:
- constructing a memory configuration table adapted to describe size and visibility attributes of a plurality of memory regions, the visibility attributes corresponding to accessibility of each of the plurality of memory regions via at least one bus of a plurality of buses;
- computing a range of memory addresses accessible over the at least one bus for each of the plurality of memory regions;
- and
- setting registers of the auxiliary processor to map memory according to the size, visibility attributes and range of memory addresses for each of the plurality of memory regions.
Dependencies are inferred from the claim text.