System latency levelization for read data
AssigneeMicron Technology, Inc.
InventorsJeffery W. Janzen, Brent Keeth, Kevin J. Ryan, Troy A. Manning, Brian Johnson
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Abstract
In a high speed memory subsystem differences in each memory device's minimum device read latency and differences in signal propagation time between the memory device and the memory controller can result in widely varying system read latencies. The present invention equalizes the system read latencies of every memory device in a high speed memory system by comparing the differences in system read latencies of each device and then operating each memory device with a device system read latency which causes every device to exhibit the same system read latency.
Claims45
A memory device comprising:
- a memory array;
- a control circuit coupled to the memory array;
- at least one of configuration line coupled to said control circuit;
- wherein said control circuit operates the memory device at a selected device read latency based upon a state of a signal asserted on said at least one configuration line.
A memory module comprising:
- a plurality of memory devices;
- and
- a register for providing configuration information to said plurality of memory devices;
- wherein each of said memory device further comprises,
- a memory array;
- a control circuit coupled to the memory array;
- at least one of configuration line coupled to said register and said control circuit;
- wherein said control circuit operates the memory device at a selected device read latency based upon a state of a signal asserted on said at least one configuration line.
A method of operating a memory device, the memory device having at least one configuration line, comprising:
- operating the memory device at a selected device read latency based upon a state of a signal asserted on said at least one configuration line.
A computer system comprising:
- a processor;
- a memory controller coupled to the processor;
- at least one memory module coupled to the memory controller, each of said memory modules comprising a plurality of memory devices;
- wherein each of said memory devices further comprises,
- a memory array;
- a control circuit coupled to the memory array;
- at least one configuration line coupled to said control circuit;
- wherein said control circuit operates the memory device at a selected device read latency based upon a state of a signal asserted on said at least one configuration line.
A method of operating a memory system, the memory system having at a plurality of memory devices and a memory controller, comprising the steps of:
- responsive to a command from the memory controller, setting each of the plurality of memory devices to operate at its minimum device read latency;
- measuring the system read latency for each of the plurality of memory devices at said memory controller;
- determining a maximum system read latency at said memory controller, said maximum system read latency being equal to the maximum of the plurality of system read latencies;
- calculating a plurality of offsets at said memory controller, each of said plurality of offsets being associated with a corresponding one of the plurality of memory devices and being equal to the difference between the maximum system read latency and the system read latency of the corresponding one of the plurality of memory devices;
- and
- setting each of the plurality of memory devices to operate at an increased device read latency by the memory controller, wherein the amount of increased device read latency is equal to the offset associated with that one of the plurality of memory devices.
Dependencies are inferred from the claim text.