DDR SDRAM memory controller with multiple dependency request architecture and intelligent requestor interface

Abstract

A controller for a double data rate synchronous dynamic random access memory (SDRAM) includes an address storage block comprising an address storage register for each of a plurality of priority levels for receiving a memory address of a request from an incoming command queue for each of a plurality of priority levels and a priority logic block coupled to the address storage block wherein the priority logic block comprises a first priority register for storing a register number field for each of the plurality of priority levels, a second priority register for storing a request valid field for each of the plurality of priority levels, and a third priority register for storing a state machine address field for each of the plurality of priority levels.

Dependencies are inferred from the claim text.