US 2004/0107310 A1Published application

Method and related apparatus for maintaining data stored in a dynamic random access memory

AssigneeVIA Technologies, Inc.

InventorI-Ming Lin

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Abstract

A method and related apparatus for maintaining stored data in a dynamic random access memory includes a processor, a dynamic random access memory (DRAM), a south bridge chipset, and a rechargeable battery device. The south bridge chipset includes a system controller, a buffer, a memory controller, an integrated device electronics controller, and a data conversion circuit. The data conversion circuit converts a hard-disk access command transmitted from the system controller into a memory access command of the memory controller. The memory controller accesses the buffer and the DRAM by executing a memory access command. When the computer system enters a power-saving mode, a switch is turned on allowing the battery device to constantly self-refresh the DRAM for maintaining the data stored in the DRAM. When the computer system powers up, the switch is turned off and the battery device is re-charged.

Claims23

Dependent claims

A computer system, the computer system comprising:

a processor for controlling operations of the computer system;
a dynamic random access memory (DRAM) electrically connected to the processor for storing data;
a south bridge chipset electrically connected to the processor and the DRAM, the south bridge chipset comprising:
a system controller for controlling operations of the south bridge chipset;
a buffer for temporarily storing the data;
a memory controller for accessing the data in the DRAM;
an integrated device electronics controller (IDE controller) for accessing data in an integrated device electronics (IDE) component;
and
a data conversion circuit electrically connected to the memory controller and the IDE controller for converting a hard-disk access command transmitted from the system controller to the IDE controller into a memory access command of the memory controller wherein the memory controller accesses the buffer and the DRAM by executing the memory access command;
a power supply for generating a plurality of operating voltages to drive the computer system;
and
a battery device for generating the operating voltages that self-refresh the DRAM;
wherein when the computer system performs a power supply management operation consistent with an advanced mode and an advanced configuration and power interface (ACPI) and enters a power-saving mode, the computer system can make use of the battery device to constantly self-refresh the DRAM for maintaining the data stored in the DRAM.

10 more elements

Dependencies are inferred from the claim text.

Facts

Application: 10/604,268Filed 8 Jul 2003
Priority: TW 0911229203 Oct 2002
Published: 3 Jun 2004
Term ends: Not estimatedThe source records don’t support an estimate.

Classification8 codes

G06F 1/30
Power supply means, e.g. regulation thereof: means for acting in the event of power-supply failure or interruption, e.g. power-supply fluctuations
G11C 7/20
Arrangements for writing information into, or reading information out from, a digital store: memory cell initialisation circuits, e.g. when…
G11C 11/406
Forming cells needing refreshing or charge regeneration, i.e. dynamic cells: management or control of the refreshing or charge-regeneration cycles
G11C 11/40615
Management or control of the refreshing or charge-regeneration cycles: internal triggering or timing of refresh, e.g. hidden refresh, self…