US 2004/0107233 A1 · Serial finite field multiplier

Abstract

The present invention relates to a finite field multiplier used for implementing an encrypting algorithm circuit, thereby minimizing power consumption and circuit area in implementing the finite field multiplier with a LFSR (Linear Feedback Shift Register) structure. The Finite field multiplier of the present invention is an operator performing a modular operation on the multiplication result of two data represented on a polynomial basis in a Galois Field into an irreducible polynomial. The LFSR structure is a serial finite field multiplication structure, and has a merit over an array structure and a hybrid structure in application to systems that are limited in size and power due to its simplicity of circuits and also its capability of being implemented in a small size.

Claims8

Dependent claims

A finite field multiplier comprising:

a first shift register for shifting first input value of m bits to right by one bit in accordance with first to third clocks;
a second shift register for shifting second input value of m bits to right by one bit in accordance with the first to third clocks;
and
logic gates for performing a logic AND operation on the first input value and the second input value for each bit;
and
a m-bit register for generating a multiplication result by adding an output value of each of the logic gates to a value of each bit and for storing the multiplication result.

3 more elements

Dependencies are inferred from the claim text.

Serial finite field multiplier

Life of this patent

Serial finite field multiplier

Life of this patent

Abstract

Claims8