Logic simulation apparatus for performing logic simulation in high speed
AssigneeRenesas Technology Corp.
InventorsAkira Yoshida, Masanori Kurimoto
Life of this patent
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Abstract
A logic simulation apparatus is provided with a circuit dividing unit (6) that selects and defines logic cones each of which carries out a logic operation in synchronization with one clock domain as target portions to be speeded up from logic cones extracted by a logic cone extracting unit (5), and that defines logic cons each of which carries out a logic operation based on a plurality of clock domains as nontarget portions not to be speeded up, and a logic compressing unit (7) that compresses the logic of each of the target portions, and performs a logic simulation on each of the target portions whose logic is compressed and also on performs a logic simulation on each of the nontarget portions.
Claims7
A logic simulation apparatus comprising:
- extracting means for extracting clock domains and logic cones from a netlist representing connections among logic cells;
- defining means for selecting and defining, as target portions to be speeded up, logic cones each of which carries out a logic operation in synchronization with one clock domain from the logic cones extracted by said extracting means, and for defining logic cones each of which carries out a logic operation based on a plurality of clock domains as nontarget portions not to be speeded up;
- logic compressing means for compressing a logic of each of the target portions;
- and
- verification means for performing a logic simulation on each of the target portions whose logic is compressed by said logic compressing means, and for performing a logic simulation on each of the nontarget portions.
Dependencies are inferred from the claim text.