Method for minimizing slip line faults on a semiconductor wafer surface
AssigneeS.O.I.Tec Silicon on Insulator Technologies
InventorsEric Neyret, Christophe Maleville, Ludovic Ecarnot
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AssigneeS.O.I.Tec Silicon on Insulator Technologies
InventorsEric Neyret, Christophe Maleville, Ludovic Ecarnot
Estimating the term…
A method for minimizing slip line faults on a surface of a semiconductor wafer that has been obtained using a transfer technique. The method includes heating the semiconductor wafer from an ambient temperature to a first higher temperature and pausing the heating at the first higher temperature for a time sufficient to stabilize the wafer. Then the wafer is heated further from the first higher temperature to a target higher temperature during a predetermined time interval. The further heating during an initial portion of the time interval is conducted at a relatively low heating rate and the heating during a final portion of the time interval is conducted at a relatively higher heating rate to thus minimize slip line faults in the surface of the wafer.
A method for minimizing slip line faults on a surface of a semiconductor wafer that has been obtained using a transfer technique, which comprises:
A method for minimizing slip line faults on a surface of a semiconductor wafer that has been obtained using a transfer technique, which comprises:
In a method for minimizing slip line faults on a surface of a semiconductor wafer that has been obtained using a transfer technique, wherein the wafer has been heated from an ambient temperature to a first higher temperature and a pause has been taken at the first higher temperature for a time sufficient to stabilize the wafer, the improvement comprising further heating the wafer from the first higher temperature to a target higher temperature during a predetermined time interval, with the further heating during an initial portion of the time interval being conducted at a relatively low heating rate and heating during a final portion of the time interval being conducted at a relatively higher heating rate to thus minimize slip line faults in the surface of the wafer.
Dependencies are inferred from the claim text.