Novel method to fabricate high reliable metal capacitor within copper back-end process

A method for the creation of a metal capacitor, comprising:

• providing a substrate, semiconductor devices having been created in or over the surface of said substrate;
• depositing a first layer of capacitor plate material over the substrate, said first layer of capacitor plate material comprising copper diffusion barrier material;
• depositing a layer of capacitor dielectric material over the first layer of capacitor plate material;
• depositing a second layer of capacitor plate material over the capacitor dielectric material, said second layer of capacitor plate material comprising copper diffusion barrier material;
• patterning and etching said second layer of capacitor plate material, said layer of capacitor dielectric material and said first layer of capacitor plate material;
• depositing a layer of spacer material over the substrate, thereby including the patterned and etched second layer of capacitor plate material, the layer of capacitor dielectric material and the first layer of capacitor plate material;
• and
• etching said layer of spacer material.

A method for the creation of a metal capacitor, comprising:

• providing a substrate, semiconductor devices having been created in or over the surface of said substrate;
• depositing a first layer of copper diffusion barrier material over the substrate;
• depositing a layer of silicon dioxide over the first layer of copper diffusion barrier material;
• depositing a second layer of copper diffusion barrier material over the layer of silicon dioxide;
• patterning and etching said second layer of copper diffusion barrier material, said layer of silicon dioxide and said first layer of copper diffusion barrier material;
• depositing a layer of PECVD silicon dioxide over the substrate, thereby including the patterned and etched second layer of copper diffusion barrier material, the layer of silicon dioxide and the first layer of copper diffusion barrier material;
• and
• etching said layer of PECVD silicon dioxide.

A method for the creation of a metal capacitor, comprising:

• providing a substrate, semiconductor devices having been created in or over the surface of said substrate;
• creating at least one first layer of patterned and etched interconnect first metal over the surface of said substrate, said at least one first layer of patterned and etched interconnect first metal comprising at least one point of electrical contact in the surface thereof;
• creating at least one metal interconnect aligned with said at least one point of electrical contact provided in the surface of said at least one first layer of interconnect first metal;
• creating at least one metal capacitor over the surface of said least one metal interconnect;
• creating a layer of spacer material over sidewalls of said at least one metal capacitor;
• and
• creating at least one second layer of patterned and etched interconnect second metal over the surface of said layer of spacer material, said least one second layer of patterned and etched interconnect second metal contacting said at least one metal capacitor.

A method for the creation of a metal capacitor, comprising:

• providing a substrate, semiconductor devices having been created in or over the surface of said substrate;
• creating at least one first layer of patterned and etched interconnect first metal over the surface of said substrate, said at least one first layer of patterned and etched interconnect first metal comprising at least one point of electrical contact in the surface thereof;
• creating at least one metal interconnect aligned with said at least one point of electrical contact provided in the surface of said at least one first layer of interconnect first metal;
• depositing a layer of etch stop material over said at least one metal interconnect;
• depositing a first layer of copper barrier material over said layer of etch stop material;
• depositing a layer of capacitor dielectric material over the surface of said first layer of copper barrier material;
• depositing a second layer of copper barrier material over the surface of said layer of capacitive dielectric material;
• patterning and etching said first layer of copper barrier material, said layer of capacitor dielectric material and said second layer of copper barrier material;
• creating a layer of spacer material over sidewalls of said patterned and etched first layer of copper barrier material, said layer of capacitor dielectric material and said second layer of copper barrier material;
• and
• creating at least one second layer of patterned and etched interconnect second metal over the surface of said layer of spacer material, said least one second layer of patterned and etched interconnect second metal contacting said at least one metal capacitor.

A capacitor created over a substrate, comprising:

• a substrate, semiconductor devices having been created in or over the surface of said substrate;
• a first layer of capacitor plate material having been deposited over the substrate, said first layer of capacitor plate material comprising copper diffusion barrier material;
• a layer of capacitor dielectric material having been deposited over the first layer of capacitor plate material;
• a second layer of capacitor plate material having been deposited over the capacitor dielectric material, said second layer of capacitor plate material comprising copper diffusion barrier material;
• said second layer of capacitor plate material, said layer of capacitor dielectric material and said first layer of capacitor plate material having been patterned and etched;
• and
• spacers having been created over sidewalls of the capacitor.

A capacitor created over a substrate, comprising:

• a substrate, semiconductor devices having been created in or over the surface of said substrate;
• a first layer of capacitor plate material having been deposited over the substrate, said first layer of capacitor plate material comprising copper diffusion barrier material;
• a layer of capacitor dielectric material having been deposited over the first layer of capacitor plate material;
• a second layer of capacitor plate material having been deposited over the capacitor dielectric material, said second layer of capacitor plate material comprising copper diffusion barrier material;
• said second layer of capacitor plate material, said layer of capacitor dielectric material and said first layer of capacitor plate material having been patterned and etched;
• a layer of spacer material having been deposited over the substrate, thereby including the patterned and etched second layer of capacitor plate material, the layer of capacitor dielectric material and the first layer of capacitor plate material;
• and
• said layer of spacer material having been etched.