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US 2004/0106253 A1Published application
Semiconductor processing methods of forming integrated circuitry
AssigneeMicron Technology, Inc.
InventorLuan C. Tran
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AssigneeMicron Technology, Inc.
InventorLuan C. Tran
Estimating the term…
Semiconductor processing methods of forming integrated circuitry are described. In one embodiment, memory circuitry and peripheral circuitry are formed over a substrate. The peripheral circuitry comprises first and second type MOS transistors. Second type halo implants are conducted into the first type MOS transistors in less than all of the peripheral MOS transistors of the first type. In another embodiment, a plurality of n-type transistor devices are formed over a substrate and comprise memory array circuitry and peripheral circuitry. At least some of the individual peripheral circuitry n-type transistor devices are partially masked, and a halo implant is conducted for unmasked portions of the partially masked peripheral circuitry n-type transistor devices. In yet another embodiment, at least a portion of only one of the source and drain regions is masked, and at least a portion of the other of the source and drains regions is exposed for at least some of the peripheral circuitry n-type transistor devices. A halo implant is conducted relative to the exposed portions of the source and drain regions. In another embodiment, a common masking step is used and a halo implant is conducted of devices formed over a substrate comprising memory circuitry and peripheral circuitry sufficient to impart to at least three of the devices three different respective threshold voltages.
A semiconductor processing method of forming integrated circuitry comprising:
In a common masking step and in a common implant step, conducting a halo implant of devices formed over a substrate comprising memory circuitry and peripheral circuitry sufficient to impart to at least three of the devices three different respective threshold voltages.
In a common masking step and in a common implant step, conducting a halo implant of devices formed over a substrate comprising memory circuitry and peripheral circuitry sufficient to impart to at least three of the devices three different respective threshold voltages, at least some of the devices forming memory access devices.
A semiconductor processing method of forming integrated circuitry comprising:
A semiconductor processing method of forming integrated circuitry comprising:
A semiconductor processing method of forming integrated circuitry comprising:
A method of improving DRAM storage cell retention time comprising conducting, in a common masking step and in a common implant step, a halo implant of devices formed over a substrate comprising memory circuitry and peripheral circuitry sufficient to impart to each device one of two or more different respective threshold voltages, at least some of the devices forming memory access devices, wherein the at least some of the devices forming memory access devices receive halo implants on a bit line contact side of the devices.
A method of improving DRAM storage cell retention time comprising forming memory access devices having different implants and hence different junction structures on a bitline contact side and a storage node side respectively.
Dependencies are inferred from the claim text.