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US 2004/0106251 A1Published application
Technique to control tunneling currents in DRAM capacitors, cells, and devices
AssigneeMicron Technology, Inc.
InventorsLeonard Forbes, Salman Akram
Life of this patent
Estimating the term…
Abstract
Structures and methods are provided for the use with PMOS devices. Materials with large electron affinities or work functions are provided for structures such as gates. A memory cell is provided that utilizes materials with work functions larger than n-type doped polysilicon (4.1 eV) or aluminum metal (4.1 eV) for gates or capacitor plates.
Claims21
A method for operating a memory cell, comprising:
- applying a negative voltage to a gate of a PMOS transistor formed in an n-type well, wherein the PMOS transistor includes:
- first source/drain region;
- a second source/drain region, wherein the first and the second source/drain region include source/drain regions having a work function greater than 4.1 eV;
- a channel located between the first and the second source/drain regions;
- a gate opposing the channel, wherein the gate includes a gate having a work function greater than 4.1 eV;
- a gate insulator separating the gate from the channel, wherein the gate insulator is less than 20 Angstroms thick;
- coupling the n-type well to a positive voltage which is less than a power supply voltage;
- and
- reading a charge level of a storage device, wherein the storage device includes a first and a second storage node, the first and the second storage nodes having a work function greater than 4.1 eV.
6 more elements
A method for operating a memory cell, comprising:
- applying a negative voltage to a gate of a PMOS transistor formed in an n-type well, wherein the PMOS transistor includes:
- first source/drain region;
- a second source/drain region, wherein the first and the second source/drain region include source/drain regions having a work function greater than 4.1 eV;
- a channel located between the first and the second source/drain regions;
- a gate opposing the channel, wherein the gate includes a gate having a work function greater than 4.1 eV;
- a gate insulator separating the gate from the channel, wherein the gate insulator is less than 20 Angstroms thick;
- coupling the n-type well to a voltage which is equal to a power supply voltage;
- and
- reading a charge level of a storage device, wherein the storage device includes a first and a second storage node, the first and the second storage nodes having a work function greater than 4.1 eV.
6 more elements
A method for operating a memory cell, comprising:
- applying a negative voltage to a gate of a PMOS transistor formed in an n-type well, wherein the PMOS transistor includes:
- first source/drain region;
- a second source/drain region, wherein the first and the second source/drain region include source/drain regions having a work function greater than 4.1 eV;
- a channel located between the first and the second source/drain regions;
- a gate opposing the channel, wherein the gate includes a gate having a work function greater than 4.1 eV;
- a gate insulator separating the gate from the channel, wherein the gate insulator is less than 20 Angstroms thick;
- coupling the n-type well to a voltage which is greater than a power supply voltage;
- and
- reading a charge level of a storage device, wherein the storage device includes a first and a second storage node, the first and the second storage nodes having a work function greater than 4.1 eV.
6 more elements
A method for operating a memory cell, comprising:
- activating a gate of a PMOS transistor formed in an n-type well, wherein the PMOS transistor includes:
- first source/drain region;
- a second source/drain region, wherein the first and the second source/drain region include source/drain regions formed from a material having a work function greater than 4.1 eV;
- a channel located between the first and the second source/drain regions;
- a gate opposing the channel, wherein the gate includes a gate formed from a silicon compound having a work function greater than 4.1 eV;
- and
- a gate insulator separating the gate from the channel,
- applying a voltage to the n-type well;
- and
- reading a charge level of a storage device coupled to the second source/drain region.
7 more elements
A method for operating a memory cell, comprising:
- activating a gate of a PMOS transistor formed in an n-type well, wherein the PMOS transistor includes:
- first source/drain region;
- a second source/drain region, wherein the first and the second source/drain region include source/drain regions formed from a material having a work function greater than 4.1 eV;
- a channel located between the first and the second source/drain regions;
- a gate opposing the channel, wherein the gate includes a gate formed from a metal having a work function greater than 4.1 eV;
- and
- a gate insulator separating the gate from the channel, applying a voltage to the n-type well;
- and
- reading a charge level of a storage device coupled to the second source/drain region.
6 more elements
A method for operating a memory cell, comprising:
- activating a gate of a PMOS transistor formed in an n-type well, wherein the PMOS transistor includes:
- first source/drain region;
- a second source/drain region, wherein the first and the second source/drain region include source/drain regions formed from a material having a work function greater than 4.1 eV;
- a channel located between the first and the second source/drain regions;
- a gate opposing the channel, wherein the gate includes a gate formed from a metal nitride having a work function greater than 4.1 eV;
- and
- a gate insulator separating the gate from the channel,
- applying a voltage to the n-type well;
- and
- reading a charge level of a storage device coupled to the second source/drain region.
7 more elements
A method for operating a memory cell, comprising:
- activating a gate of a PMOS transistor formed in an n-type well, wherein the PMOS transistor includes:
- first source/drain region;
- a second source/drain region, wherein the first and the second source/drain region include source/drain regions formed from a first doped semiconductor material having a work function greater than 4.1 eV;
- a channel located between the first and the second source/drain regions;
- a gate opposing the channel, wherein the gate includes a gate formed from a second doped semiconductor material having a work function greater than 4.1 eV;
- and
- a gate insulator separating the gate from the channel,
- applying a voltage to the n-type well;
- and
- reading a charge level of a storage device coupled to the second source/drain region.
7 more elements
Dependencies are inferred from the claim text.