Back to results
US 2004/0106250 A1Published application
Method of fabricating semiconductor integrated circuit device
AssigneeHitachi, Ltd.
InventorsShinji Nishihara, Shuji Ikeda, Naotaka Hashimoto, Hiroshi Momiji, Hiromi Abe, Shinichi Fukada, Masayuki Suzuki
Life of this patent
Estimating the term…
Abstract
A Co silicide layer having a low resistance and a small junction leakage current is formed on the surface of the gate electrode, source and drain of MOSFETs by silicidizing a Co film deposited on a main plane of a wafer by sputtering using a high purity Co target having a Co purity of at least 99.99% and Fe and Ni contents of not greater than 10 ppm, preferably having a Co purity of 99.999%.
Claims8
A method of fabricating a semiconductor integrated circuit device, comprising the steps of:
- (a) forming two gate electrodes to be N- and P-type gate electrodes respectively over first and second regions of a silicon surface, each of said two gate electrodes having a silicon film to be a polysilicon conductive film;
- (b) forming N-type source and drain regions in the first region, said N-type source and drain regions constituting a first insulated gate field effect transistor together with the N-type gate electrode;
- (c) forming P-type source and drain regions in the second region, said P-type source and drain regions constituting a second insulated gate field effect transistor together with the P-type gate electrode doped with boron;
- (d) depositing a Co film on the silicon surface over said N-type and P-type source regions and drain regions, and upper surfaces of said N- and P-type gate electrodes respectively isolated from said N-type and P-type source regions and drain regions with insulating side walls, by sputtering, from a Co sputtering target which, apart from carbon and oxygen impurities, is at least 99.99 wt. % pure, and wherein a sum of Fe and Ni in the Co sputtering target is not greater than 50 ppm by weight, wherein the sputtering is performed in such a manner that the composition of the deposited Co film is substantially the same as that of the Co sputtering target;
- (e) performing first rapid thermal annealing at a first temperature to the silicon surface covered with the Co film so as to form Co monosilicide films on the silicon surface and the upper surfaces, leaving a remaining Co film not formed into Co monosilicide, wherein the first temperature is a temperature that creep-up across the insulating side walls substantially does not take place;
- (f) removing the remaining Co film, remaining over the first major surface, by wet etching;
- and
- (g) after step (f), performing second rapid thermal annealing at a second temperature higher than the first temperature so as to form Co disilicide films on the silicon surface and the upper surfaces.
5 more elements
Dependencies are inferred from the claim text.