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US 2004/0106249 A1Published application
Method to fabricate dual metal CMOS devices
AssigneeASM International N.V.
InventorHannu Huotari
Life of this patent
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Abstract
The present invention relates generally to barrier layers in transistor gate stacks in integrated circuits, and to processes for forming such gate stacks.
Claims42
A gate stack in an integrated circuit comprising a PMOS region, an NMOS region, a dielectric layer, and a barrier layer, wherein the barrier layer overlies both the PMOS region and the NMOS region.
A method of forming a gate stack in an integrated circuit comprising:
- depositing a dielectric layer over a substrate comprising a first region and a second region;
- depositing a barrier layer directly over the dielectric layer such that it overlies both the first and second regions;
- and
- forming a first gate electrode layer over the first region of the substrate and a second gate electrode layer over the second region.
1 more element
A method of forming a first and second electrode in an integrated circuit comprising:
- depositing a dielectric layer over a substrate comprising a first region and a second region;
- depositing a barrier layer directly over the dielectric layer such that it overlies the first and second regions;
- depositing a first gate electrode material over the first and second regions of the substrate;
- removing first gate electrode material from over the first region without removing the barrier layer;
- and
- depositing a second gate electrode material over the substrate, and
- defining a first and second electrode in the first and second region.
4 more elements
Dependencies are inferred from the claim text.