[pixel structure and fabricating method thereof]

A method of forming a pixel structure, comprising the steps of:

• forming a gate and a scan line having connection with the gate over a substrate;
• forming an insulation layer over the substrate covering the gate and the scan line;
• forming a channel material layer over the insulation layer;
• forming a metallic layer over the channel layer;
• forming a patterned first photoresist layer over the metallic layer;
• patterning the metallic layer using the first photoresist layer as a mask to form a data line and a source/drain metallic layer;
• patterning the channel material layer using the first photoresist layer as a mask to form a channel layer;
• patterning the source/drain metallic layer using the first photoresist layer as a mask to form source/drain terminals, wherein the source terminal and the data line are electrically connected, and the gate, the channel layer and the source/drain terminals together constitute a thin film transistor;
• removing the first photoresist layer;
• forming a passivation layer over the substrate covering the thin film transistor;
• forming a second photoresist layer over the passivation layer;
• conducting a back exposure process using the gate, the source/drain terminals, the scan line and the data line as a mask and chemically developing the second photoresist layer to form a patterned second photoresist layer;
• patterning the passivation layer and the insulation layer using the patterned second photoresist layer as a mask to expose a sidewall of the source/drain terminal;
• removing the patterned second photoresist layer;
• and
• forming a pixel electrode over the passivation layer, wherein the pixel electrode and the drain terminal are electrically connected through a sidewall of the drain terminal.

A pixel structure over a substrate, the pixel structure comprising:

• a thin film transistor over the substrate, the thin film transistor having a gate, a channel layer and a pair of source/drain terminals;
• a scan line over the substrate, the scan line and the gate being electrically connected;
• a data line over the substrate, the data line and the source terminal being electrically connected;
• an insulation layer over the substrate only in areas having the gate, the source/drain terminals, the data line and the scan line thereon, and the insulation layer covering the gate and the scan line;
• a passivation layer over the substrate only in areas having the gate, the source/drain terminals, the data line and the scan line, and the passivation layer covering the source/drain terminals and the data line, wherein a sidewall of the source/drain terminal is exposed;
• and
• a pixel electrode over the substrate, the pixel electrode being positioned close to the thin film transistor such that the pixel electrode and a sidewall of the drain terminal of the thin film transistor are electrically connected.