Method to manufacture LDMOS transistors with improved threshold voltage control
AssigneeTexas Instruments Incorporated
InventorsBinghua Hu, Howard S. Lee, Henry L. Edwards, John Lin, Vladimir N. Bolkhovsky
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Abstract
A double diffused region (65), (75), (85) is formed in an epitaxial layer (20). The double diffused region is formed by first implanting light implant specie such as boron through an opening in a photoresist layer prior to a hard bake process. Subsequent to a hard bake process heavy implant specie such as arsenic can be implanted into the epitaxial layer. During subsequent processing such as LOCOS formation the double diffused region is formed. A dielectric layer (120) is formed on the epitaxial layer (20) and gate structures (130), (135) are formed over the dielectric layer (120).
Claims10
A method for forming a doped region in a semiconductor substrate, comprising:
- providing a semiconductor;
- forming a patterned photoresist layer comprising at least one opening on said semiconductor;
- implanting a first species into said semiconductor through said opening;
- performing a hard bake on said patterned photoresist layer;
- and
- implanting a second species into said semiconductor through said opening.
A method for forming a double diffused region, comprising:
- providing a semiconductor;
- forming a patterned photoresist layer over said semiconductor wherein said patterned photoresist layer comprises at least one opening;
- implanting a boron species into a region of said semiconductor through said opening;
- performing a hard bake process on said patterned photoresist layer;
- implanting an arsenic species into said region of said semiconductor through said opening;
- and
- performing at least one thermal annealing cycle on said semiconductor.
A method for forming a LDMOS transistor, comprising:
- forming an epitaxial layer on a semiconductor substrate;
- forming a deep n-well region in said epitaxial layer;
- forming a patterned photoresist layer over said deep n-well region wherein said patterned photoresist layer comprises at least one opening;
- implanting a boron species into said deep n-well through said opening;
- performing a hard bake process on said patterned photoresist layer;
- implanting an arsenic species into said deep n-well through said opening;
- forming LOCOS isolation structures in said deep n-well region;
- and
- forming a gate dielectric layer on said deep n-well region.
Dependencies are inferred from the claim text.