Digital-data receiver synchronization
AssigneeUT-Battelle, LLC
InventorsStephen F. Smith, Gary W. Turner
Life of this patent
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Abstract
An improved digital-data receiver synchronization apparatus and method is provided wherein memory devices in the receiver such as phase-lock loops are provided with composite phase-frequency detectors, mutually cross-connected comparison feedback means, or both to provide robust reception of digital data signals. The apparatus and method are preferrably utilized with synchronous architecture wherein a single master clock is used to provide frequency signals to the memory devices, and also can be used with asynchronous architecture. The apparatus and method provide fast lock-up times in moderately to severely noisy conditions and have improved tolerances to clock asymmetries.
Claims29
An improved digital-data receiver synchronization apparatus comprising:
- a plurality of memory devices for receiving multiple timing signals;
- and
- feedback means interconnecting said memory devices and cross-coupling signals produced by said memory devices.
An improved digital-data receiver synchronization apparatus comprising:
- a plurality of memory devices for receiving multiple timing signals, at least one of said plurality of memory devices comprising a composite phase-frequency detector;
- a common frequency reference source in communication with said plurality of memory devices for driving said plurality of memory devices;
- and,
- a feedback means interconnecting said memory devices and for cross-coupling certain signals produced by said memory devices.
An improved digital data receiver synchronization apparatus for receiving data signals
- from a transmitter, said apparatus comprising:
- first synchronization means for synchronizing a first frequency signal with a first received data signal and for generating a first comparison signal;
- second synchronization means for synchronizing a second frequency signal with a second received data signal and for generating a second comparison signal;
- first interconnection means for transmitting said first comparison signal to said second synchronization means;
- second interconnection means for transmitting said second comparison signal to said first synchronization means;
- said first synchronization means comprising a first corrective means for adjusting said first frequency signal in response to said second comparison signal;
- and
- said second synchronization means comprising a second corrective means for adjusting said second frequency signal in response to said first comparison signal.
The method of providing improved digital-data receiver synchronization comprising the steps of:
- providing a plurality of memory devices for receiving multiple timing signals, at least one of said plurality of memory devices comprising a composite phase-frequency detector, each of said plurality of memory devices providing an output comparison signal;
- and,
- interconnecting said memory devices with a feedback means for cross-coupling said output comparison signals produced by said memory devices.
A method of providing improved digital-data receiver synchronization of received data signals comprising the steps of:
- providing a first synchronization means for synchronizing a first frequency signal with a first received data signal and for generating a first comparison signal;
- providing a second synchronization means for synchronizing a second frequency signal with a second received data signal and for generating a second comparison signal;
- transmitting said first comparison signal to said second synchronization means;
- transmitting said second comparison signal to said first synchronization means;
- adjusting said first frequency signal in response to said second comparison signal;
- and
- adjusting said second frequency signal in response to said first comparison signal.
Dependencies are inferred from the claim text.