US 2004/0105508 A1Published application

Apparatus and method for synchronizing symbol timing using timing loop controller

AssigneeElectronics and Telecommunications Research Institute

InventorsPanSoo Kim, Young Wan Kim, Nae-Soo Kim

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Abstract

A timing loop controller for multilevel modulation scheme is disclosed. The timing loop controller includes a first to fourth computing unit for computing a timing error between an input timing of digital signals and a sampling timing; a first to fourth quantization unit for controlling a direction and an error value of the timing error; a first and second sign detection unit for detecting sign change according to results; a zero crossing detection unit for detecting zero crossing at I axis and Q axis; and a timing error control unit for controlling the timing error value in case there is no sign change. The present invention can increase a zitter performance of timing error according to the signal-to-noise ratio by detecting the timing error, outputting the timing error and controlling the timing error output value only in case there is sign change by additionally equipping the sign variation detector.

Claims11

Dependent claims

A timing loop controller for multilevel modulation scheme, comprising:

a first buffer for orderly receiving I-channel digital signals and generating first buffered signals by buffering the received I-channel digital signals;
a second buffer for receiving the received I-channel digital signals from the first buffer and generating second buffered digital signals;
a first quantization means for receiving the buffered digital signals from the second buffer and generating first quantized signals by quantizing the second buffered digital signals;
a second quantization means for receiving the I-channel digital signals and generating second quantized signals by quantizing the I-channel digital signals;
a first sign detection means for receiving the first quantized signals and the second quantized signals and detecting sign change of the first quantized signals and the second quantized signals;
a third buffer for orderly receiving Q-channel digital signals and generating a third buffered signals by buffering the received Q-channel digital signals;
a fourth buffer for receiving the received Q-channel digital signals from the first buffer and generating fourth buffered digital signals;
a third quantization means for receiving the fourth buffered digital signals from the fourth buffer and generating third quantized signals by quantizing the fourth buffered digital signals;
a fourth quantization means for receiving the Q-channel digital signals and generating fourth quantized signals by quantizing the Q-channel digital signals;
a second sign detection means for receiving the third quantized signals and the fourth quantized signals and detecting sign change of the third quantized signals and the fourth quantized signals;
a timing error computation means for computing a timing error output value based on the I-channel digital signals, the first buffered signals, the first quantized signals, the Q-channel digital signals, the third buffered signals, the third quantized signals and the fourth quantized signals;
a zero crossing detection means for detecting zero crossing at I axis and Q axis according based on results outputted from the first and second sign detection means;
and
a timing error control means for controlling the timing error value in case there is no sign change according to results outputted from the first and second sign detection means.

11 more elements

A symbol timing synchronizer using a timing synchronous loop controller for multilevel modulation scheme, comprising:

A/D conversion means for converting successively inputted analogue signals to digital signals;
timing error detection means for calculating an timing error between an input timing of the digital signal successively inputted from the A/D conversion means and a sampling timing of the A/D conversion means and detecting sign change of the digital signals;
timing error output control means for outputting the timing error calculated from the timing error detection means and controlling the timing error output value;
filtering means for eliminating a noise of the timing error value controlled by the timing error output control means and calculating a mean value of errors;
and
timing error compensation means for compensating the timing error of the sampling timing of the A/D conversion means by shifting the sampling timing corresponding to the calculated error value from the timing error detection means.

3 more elements

Dependencies are inferred from the claim text.