Image processing system
OwnerKoji Hosogi, Kiyokazu Nishioka +3inventors
InventorsKoji Hosogi, Kiyokazu Nishioka, Yukio Fujii, Yoshifumi Fujikawa, Shigeki Higashijima
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Abstract
In a system in which a CPU 2 and a motion compensation coprocessor 1 are interconnected via a bus 3, the motion compensation coprocessor 1 has computation descriptor registers 12 that are chainable on an individual process basis, and comprises means for reading reference data in accordance with the contents of the computation descriptor registers, means for outputting a computation result, a read/storage circuit 18 for storing reference data, a write/storage circuit 19 for storing a computation result, and a motion compensation computing unit 17.
Claims9
An image processing system, comprising:
- a CPU;
- a coprocessor:
- a main storage control circuit;
- a bus for interconnecting said CPU, said coprocessor, and said main storage control circuit;
- and
- and a main storage connected to said main storage control circuit,
- wherein said CPU creates a descriptor, which includes the information describing the process used for operating said coprocessor, the address indicating the area of the data to be referenced for an individual unit of processing, the address indicating the area for computation result output, and the information necessary for each unit of processing, and stores the created descriptor in said main storage;
- and
- wherein said coprocessor reads said descriptor, reads data from said main storage in accordance with the information stored in said descriptor, and performs a computation process.
Dependencies are inferred from the claim text.