Semiconductor integrated circuit
AssigneeSeiko Epson Corporation
InventorTsuyoshi Yoneyama
Life of this patent
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Abstract
A semiconductor integrated circuit is provided which is capable of selecting lines of a data bus to which data is input when the number of bits of input data is different from the number of bits of the data bus with which to input data to be written into a RAM. The semiconductor integrated circuit comprises K-bit data bus lines D0 to D7 (K is an integer 2 or more) to which data is input; selection circuits SEL (0) to SEL (13) for selecting data input through an N number of the data bus lines on the high bit side or through an N number of the data bus lines on the low bit side based on a set signal when N-bit data is input into the data bus lines (N is an integer smaller than K); and a random access memory (RAM) 1 for storing data selected by the selection circuit.
Claims3
A semiconductor integrated circuit comprising:
- a K-bit (K is an integer not less than 2) data bus to which data is input;
- a selection circuit selecting data input through one of an N number of lines on a high bit side and an N number of lines on a low bit side of the data bus in accordance with a set signal when N-bit data (N is an integer smaller than K) is input to the data bus;
- and
- a random access memory (RAM) storing data selected by the selection circuit.
Dependencies are inferred from the claim text.