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US 2004/0105334 A1Published application
Semiconductor memory device having test mode
AssigneeRenesas Technology Corp.
InventorKenichi Yasuda
Life of this patent
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Abstract
In a burn-in test, a sense amplifier circuit is separated from each bit line by a bit line separation switch. In this state, a bit line switch circuit connects one of complementary bit lines to a first voltage node, and connects the other complementary bit line to a second voltage node in blocks on both sides. A first bit line voltage supplied by the first voltage node and a second bit line voltage supplied by the second voltage node can be set independently of each other at least in the burn-in test.
Claims7
A semiconductor memory device comprising:
- a plurality of memory cells arranged in a matrix;
- a plurality of bit line pairs provided corresponding to columns of said plurality of memory cells;
- and
- a plurality of sense amplifier units provided corresponding to said plurality of bit line pairs, respectively, wherein
- each of said plurality of bit line pairs includes a first bit line and a second bit line, and
- each of said plurality of sense amplifier units includes:
- a sense amplifier circuit connected to the corresponding first and second bit lines at least in data read;
- and
- a bit line switch for connecting the corresponding first and second bit lines to one and another one of a plurality of voltage nodes which can supply different voltages, respectively, in a test.
6 more elements
A semiconductor memory device comprising:
- a plurality of memory cells arranged in a matrix;
- a plurality of bit line pairs provided corresponding to columns of said plurality of memory cells;
- and
- a plurality of sense amplifier units provided corresponding to said plurality of bit line pairs, respectively, wherein
- each of said plurality of bit line pairs includes a first bit line and a second bit line,
- each of said plurality of sense amplifier units includes a sense amplifier circuit connected to the corresponding first and second bit lines at least in data read,
- each of the sense amplifier units corresponding to the bit line pairs in odd numbers further includes a first bit line switch for connecting the corresponding first and second bit lines to a first voltage node in a test,
- each of the sense amplifier units corresponding to the bit line pairs in even numbers further includes a second bit line switch for connecting the corresponding first and second bit lines to a second voltage node in said test, and
- voltages of said first and second voltage nodes can be set independently of each other in said test.
6 more elements
Dependencies are inferred from the claim text.