Apparatus and method for a current limiting bleeder device shared by columns of different memory arrays

A memory device, comprising:

• a first memory array having memory cells arranged in rows and columns, each of the columns having a equilibration circuit;
• a second memory array having memory cells arranged in rows and columns, each of the columns having a equilibration circuit;
• a sense amplifier region having a plurality of sense amplifiers formed therein, each sense amplifier coupled to a respective column of the first memory array and further coupled to a respective column of the second memory array;
• and
• a bleeder device formed in the sense amplifier region, and coupled to a precharge voltage supply and to the equilibration circuits of a column of the first memory array and a column of the second memory array, the columns of the first and second memory arrays coupled to the same sense amplifier.

A memory device, comprising:

• a first memory array region having formed therein memory cells arranged in rows and columns, each of the columns coupled to a respective equilibration circuit also formed in the first memory array region;
• a second memory array region having formed therein memory cells arranged in rows and columns, each of the columns coupled to a respective equilibration circuit also formed in the second memory array region;
• a sense amplifier region having formed therein sense amplifiers and a plurality of bleeder devices, each bleeder device coupled to a precharge voltage supply and further coupled to at least one equilibration circuit formed in the first memory array region and to at least one equilibration circuit formed in the second memory array region;
• and
• first and second plurality of isolation switches coupling each of the sense amplifiers formed in the sense amplifier region to respective a column of memory cells from the first memory array and to a respective column of memory cells from the second memory array.

A computer system, comprising:

• a processor having a processor bus;
• an input device coupled to the processor through the processor bus and adapted to allow data to be entered into the computer system;
• an output device coupled to the processor through the processor bus and adapted to allow data to be output from the computer system;
• and
• a memory device coupled to the processor through the processor bus, the memory device having memory cells arranged in rows and columns of memory cells, each column having an equilibration circuit for precharging the respective column, the memory device comprising a sense amplifier region having a plurality of sense amplifiers, each sense amplifier coupled to a respective one of a first plurality of columns of memory cells through a respective first isolation switch and further coupled to a respective one of a second plurality of columns of memory cells through a respective second isolation switch, the sense amplifier region further having a plurality of bleeder devices, each of the bleeder devices coupled to a precharge voltage supply and at least one equilibration circuit coupled to a column of the first plurality of columns and at least one equilibration circuit coupled to a column of the second plurality of columns to limit current drawn by the respective equilibration circuits.

A computer system, comprising:

• a processor having a processor bus;
• an input device coupled to the processor through the processor bus and adapted to allow data to be entered into the computer system;
• an output device coupled to the processor through the processor bus and adapted to allow data to be output from the computer system;
• and
• a memory device coupled to the processor through the processor bus, the memory device comprising:
• a first memory array having memory cells arranged in rows and columns, each of the columns having a equilibration circuit to precharge the respective column;
• a second memory array having memory cells arranged in rows and columns, each of the columns having a equilibration circuit to precharge the respective column;
• and
• a bleeder device coupled to a precharge voltage supply and further coupled to at least one equilibration circuit of a column in the first memory array and to at least one equilibration circuit of a column in the second memory array, the bleeder device limiting the current drawn by the equilibration circuits from the precharge voltage supply.

A method for forming a memory device, comprising:

• forming a first memory array having memory cells arranged in rows and columns, each of the columns having a equilibration circuit;
• forming a second memory array having memory cells arranged in rows and columns, each of the columns having a equilibration circuit;
• forming a sense amplifier region having a plurality of sense amplifiers formed therein, each sense amplifier coupled to a respective column of the first memory array and further coupled to a respective column of the second memory array;
• and
• forming a bleeder device in the sense amplifier region coupled to a precharge voltage supply and coupling the bleeder device to the equilibration circuits of a column of the first memory array and a column of the second memory array, the columns of the first and second memory arrays coupled to the same sense amplifier.