Magnetic semiconductor memory device
AssigneeRenesas Technology Corp.
InventorsHideyuki Matsuoka, Kenchi Ito, Takeshi Sakata, Kiyoo Itoh
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Abstract
A memory cell in a so-called MRAM by utilizing a tunnel magnetic resistance in the prior art has raised problems that a magnetic field to be applied to a TMR element is essentially weak since a word line for write is disposed apart from the TMR element, that a large current is required at the time of a writing operation, and that electric power consumption is large. In order to solve the above-described problems experienced in the prior art, the present invention provides an MRAM memory cell structure and its fabricating method in which a word line for write is disposed near a TMR element and surrounds it in three directions.
Claims20
A magnetic semiconductor memory device comprising:
- a semiconductor substrate;
- first and second word lines arranged in parallel to each other on the semiconductor substrate;
- a bit line crossing the first and second word lines via an insulator layer;
- and
- a memory cell including a transistor disposed between the first word line and the bit line and a magnetic resistance element disposed between the second word line and the bit line;
- wherein the magnetic resistance element is formed into a pillar-like shape by patterning a plurality of layered structures formed on the semiconductor substrate, and at least the side surface is covered with the second word line via the insulator layer.
A magnetic semiconductor memory device comprising:
- a semiconductor substrate;
- first and second word lines arranged in parallel to each other on the semiconductor substrate;
- a bit line crossing the first and second word lines via an insulator layer;
- and
- a memory cell including a transistor disposed between the first word line and the bit line and a magnetic resistance element disposed between the second word line and the bit line;
- wherein the magnetic resistance element is formed into a pillar-like shape by patterning a plurality of layered structures formed on the semiconductor substrate, and the top surface and two side surfaces are covered with the second word line via the insulator layer.
A magnetic semiconductor memory device comprising:
- a semiconductor substrate;
- a plurality of word lines formed on the semiconductor substrate;
- a plurality of bit lines crossing the plurality of word lines;
- and
- a memory array including memory cells arranged at crossing points between the plurality of word lines and the plurality of bit lines;
- wherein the memory cell includes a vertical type transistor having a channel area formed in a direction perpendicular to the main surface of the semiconductor substrate and a magnetic resistance element disposed above the vertical type transistor, the word line being a gate electrode of the vertical type transistor and covering at least two side surfaces of the magnetic resistance element via an insulator film.
Dependencies are inferred from the claim text.