Method of manufacturing a scalable flash eeprom memory cell with floating gate spacer wrapped by control gate

A method of making a memory device on a semiconductor substrate of a first conductivity type, comprising the steps of:

• forming spaced-apart first and second regions in the substrate that have a second conductivity type different from the first conductivity type, wherein a channel region is defined in the substrate between the first and second regions;
• forming a conductive select gate over and insulated from the substrate, wherein the select gate extends over a first portion of the channel and has a first height;
• forming a conductive floating gate spacer over and insulated from the substrate, wherein the floating gate includes:
• a bottom surface extending over a second portion of the channel region, and
• first and second side surfaces extending from the bottom surface to a height greater than the first height;
• and
• forming a conductive control gate over and insulated from the floating gate, wherein the control gate includes a first portion disposed adjacent to the first floating gate side surface and a second portion disposed adjacent to the second floating gate side surface.

A method of making a memory device on a semiconductor substrate of a first conductivity type, comprising the steps of:

• forming spaced-apart first and second regions in the substrate that have a second conductivity type different from the first conductivity type, wherein a channel region is defined in the substrate between the first and second regions;
• forming a first layer of insulating material on substrate;
• forming a select gate on the first insulating layer, wherein the select gate is positioned over a first portion of said channel;
• forming a second layer of insulating material on the select gate;
• forming a layer of material on the second layer of insulating material;
• forming a floating gate spacer of conductive material adjacent to and insulated from the select gate and adjacent to the layer of material, wherein the floating gate includes:
• a bottom surface extending over a second portion of the channel region, and
• first and second side surfaces extending from the bottom surface;
• removing the layer of material;
• and
• forming a conductive control gate over and insulated from the floating gate and over the second insulating layer, wherein the control gate includes a first portion disposed adjacent to and insulated from the first floating gate side surface and a second portion disposed adjacent to and insulated from the second floating gate side surface.

An electrically erasable and programmable memory device comprising:

• a substrate of semiconductor material of a first conductivity type;
• spaced-apart first and second regions formed in the substrate and having a second conductivity type different from the first conductivity type, with a channel region therebetween;
• a conductive select gate formed over and insulated from the substrate, the select gate extending over a first portion of the channel;
• a conductive floating gate formed as a spacer over and insulated from the substrate, the floating gate including:
• a bottom surface extending over a second portion of the channel region, and
• first and second side surfaces extending from the bottom surface;
• and
• a conductive control gate formed over and insulated from the floating gate, the control gate includes:
• a first portion disposed adjacent to the first floating gate side surface, and
• a second portion disposed adjacent to the second floating gate side surface;
• wherein the control gate is formed by the process of:
• selecting a desired capacitive coupling ratio between the floating gate and the control gate;
• and
• forming the control gate second portion with a predetermined height for achieving the desired capacitive coupling ratio.