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US 2004/0105316 A1Published application
Low program power flash memory array and related control method
OwnerChing-Sung Yang, Ching-Hsiang Hsuinventors
Life of this patent
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Abstract
A flash memory array and related method for programming, erasing, and reading. The memory includes: a plurality of memory cells, each memory cell having a gate, a drain, a source, and a body; a plurality of word lines and body lines. The bodies of the memory cells whose gates are connected to a same word line are connected to a same body line, and the body lines are isolated from each other such that different body lines can be driven to have different voltages. When the memory programs, erases, and reads data, the different body lines are driven to different voltage.
Claims25
A memory comprising:
- a plurality of first memory cells;
- each first memory cell having a gate, a body, a source, and a drain;
- the gate of each first memory cell being connected to a first word line;
- the body of each first memory cell being connected to a first body line;
- wherein each first memory cell is used for storing a data bit and the first memory cell is capable of generating a current corresponding to the data bit, the current flowing across the drain of the first memory cell and the source of the first memory cell according to a voltage at the first word line;
- a plurality of second memory cells;
- each second memory cell having a gate, a body, a source, and a drain;
- the gate of each second memory cell being connected to a second word line;
- the body of each second memory cell being connected to a second body line;
- wherein each second memory cell is used for storing a data bit, and for providing a current corresponding to the data bit and flowing across the drain of the second memory cell and the source of the second memory cell according to a voltage at the second word line;
- a bit line circuit connected to the drains of the plurality of the first memory cells and to the drains of the plurality of the second memory cells;
- and
- a source circuit connected to the sources of the plurality of the first memory cells and to the sources of the plurality of the second memory cells;
- wherein the first body line is not electrically connected to the second body line to make a voltage at the first body line be different from a voltage at the second body line.
11 more elements
A method for controlling a memory;
- the memory comprising:
- a plurality of first memory cells;
- each first memory cell having a gate, a body, a source, and a drain;
- the gate of each first memory cell being connected to a first word line;
- the body of each first memory cell being connected to a first body line;
- wherein each first memory cell is used for storing a data bit, and each first memory cell is capable of generating a current corresponding to the data bit, the current flowing across the drain of the first memory cell and the source of the first memory cell when a voltage at the first word line is an access voltage;
- a plurality of second memory cells;
- each second memory cell having a gate, a body, a source, and a drain;
- the gate of each second memory cell being connected to a second word line;
- the body of each second memory cell being connected to a second body line;
- wherein each second memory cell is used for storing a data bit, the first memory cell is capable of generating a current corresponding to the data bit, the current flowing across the drain of the second memory cell and the source of the second memory cell when a voltage at the second word line is the access voltage;
- a source circuit connected to the sources of the plurality of the first memory cells and to sources of the plurality of the second memory cells for making voltages at the sources of the plurality of the first memory cells equal voltages at the sources of the plurality of the second memory cells;
- the method comprising:
- making a voltage at the first body line differ from a voltage at the second body line.
11 more elements
A method for controlling a memory;
- the memory comprising:
- a plurality of first memory cells;
- each first memory cell having a gate, a body, a source, and a drain;
- the gate of each first memory cell being connected to a first word line;
- the body of each first memory cell being connected to a first body line;
- wherein each first memory cell is used for storing a corresponding data bit;
- wherein when a voltage at the gate of the first memory cell equals a program voltage, the first memory stores a charge corresponding to the data bit of the first memory cell, and when a voltage at the first word line is an access voltage the first memory generatesa current corresponding to the data bit, the current flowing across the drain of the first memory cell and the source of the first memory cell;
- a plurality of second memory cells;
- each second memory cell having a gate, a body, a source, and a drain;
- the gate of each second memory cell being connected to a second word line;
- the body of each second memory cell being connected to a second body line;
- wherein each second memory cell is used for storing a data bit;
- wherein when a voltage at the gate of the second memory cell equals the program voltage, the second memory cell stores a charge corresponding to the data bit of the second memory cell, and when a voltage at the second word line is the access voltage, the second memory cell generates a current corresponding to the data bit, the current flowing across the drain of the second memory cell and the source of the second memory cell;
- a source circuit connected to the sources of the plurality of the first memory cells and to the sources of the plurality of the second memory cells for making a voltage at the source of each first memory cell equal a voltage at the source of the corresponding second memory cell;
- the method comprising:
- setting a voltage at the first body line to differ from a voltage at the second body line.
13 more elements
Dependencies are inferred from the claim text.