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US 2004/0105314 A1Published application
Semiconductor memory device for storing multivalued data
AssigneeKabushiki Kaisha Toshiba
InventorsNoboru Shibata, Tomoharu Tanaka
Life of this patent
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Abstract
Before the next data is stored into a first memory cell in which i bits of data have been stored, i or less bits of data are written into cells adjacent to the first memory cell beforehand. The writing of i or less bits of data is done using a threshold voltage lower than the original threshold voltage (or the actual threshold voltage in storing i bits of data). After the adjacent cells have been written into, writing is done to raise the threshold voltage of the first memory cell.
Claims30
A semiconductor memory device comprising:
- a memory cell array in which a plurality of memory cells are arranged in a matrix, each storing n-valued data (n is a natural number equal to or larger than 2);
- and
- a write circuit which writes data into each of the memory cells and which, before storing next at least one-valued data into a first memory cell in which j-valued data (j<n) has been stored in the memory cell array, writes j or less-valued data into at least one of the memory cells adjacent to the first memory cell.
A semiconductor memory device comprising:
- a memory cell array which has at least one first memory cell arranged in a matrix and at least one second memory cell selected simultaneously with the first memory cell, the first memory cell storing n-valued data (n is a natural number equal to or larger than 2);
- and
- a write circuit which, when writing next at least one-valued data into the first memory cell in which j-valued data (j<n) in the memory cell array has been stored, writes data to change the logic level of the second memory from a first logic level to a second logic level.
A semiconductor memory device comprising:
- a memory cell array which has at least one first memory cell arranged in a matrix and at least one second memory cell selected simultaneously with the first memory cell, the first memory cell storing k (k is a natural number equal to or larger than 2) bits of data;
- and
- a write circuit which, when writing next at least one bit of data into the first memory cell in which i (i<k) bits of data has been stored in the memory cell array, writes data to change the logic level of the second memory cell from a first logic level to a second logic level.
A semiconductor memory device comprising:
- a memory cell which stores k bits (k is a natural number equal to or larger than 2);
- a first storage circuit which stores an input data;
- a second storage circuit which stores the data read from the memory cell or the input data;
- and
- a control circuit which, in a write operation, holds or changes the data in the first storage circuit or the data in the second storage circuit on the basis of the data stored in the memory cell and which, in the middle of a write operation, inputs next write data to the first storage circuit, when the data stored in the first storage circuit becomes unnecessary to the write operation.
2 more elements
A semiconductor memory device comprising:
- a memory cell array which has at least one first memory cell arranged in a matrix and at least one second memory cell selected simultaneously with the first memory cell, the first memory cell storing k (k is a natural number equal to or larger than 2) bits of data;
- a write circuit which, before storing next at least one bit of data into the first memory cell in which i bits (i<k) of data has been stored in the memory cell array, writes i or less bits of data into at least one of the memory cells adjacent to the first memory cell and, when writing one bit of data into the first memory cell, writes data into the second memory cell;
- and
- a read circuit which, when outputting the data read from the first memory cell, controls the logic level of the data to be outputted on the basis of the data stored in the second memory cell.
1 more element
A semiconductor memory device comprising:
- a memory cell which stores a plurality of data items using a plurality of threshold voltages;
- a first and a second data storage circuit which are connected to bit lines and which store data of a first or a second logic level on the basis of data supplied from the outside world and the data read from the memory cell;
- a control circuit which carries out a first write operation to change the threshold voltage of the memory cell when the data in the first data storage circuit is at the first logic level, carries out a second write operation when the data in the first data storage circuit is at the second logic level and the data in the second data storage circuit is at the first logic level, and does not change the threshold voltage when the data in the first data storage circuit is at the second logic level and the data in the second data storage circuit is at the second logic level,
- which, in a first verify operation, changes the logic level of the data in the first data storage circuit to the second logic level when the data in the first data storage circuit is at the first logic level, the data in the second data storage circuit is at the first logic level, and the threshold voltage of the memory cell has reached a first verify potential, does not change the data in the first data storage circuit when the threshold voltage of the memory cell has not reached the first verify potential, does not change the data in the first data storage circuit when the data in the first data storage circuit is at the first logic level and the data in the second data storage circuit is at the second logic level, and does not change the data in the first data storage circuit and holds its logic level at the second logic level when the data in the first data storage circuit is at the second logic level, and
- which, in a second verify operation, changes the logic level of the data in the second data storage circuit to the second logic level when the data in the second data storage circuit is at the first logic level and the threshold voltage of the memory cell has reached a second verify potential, causes the data in the second data storage circuit to remain at the first logic level when the threshold voltage of the memory cell has not reached the second verify potential, and carries out a write operation until the data in the first data storage circuit has reached the second logic level and the data in the second data storage circuit has reached the second logic level.
2 more elements
Dependencies are inferred from the claim text.