US 2004/0105310 A1 · Non-volatile semiconductor storage device composed of NAND type EEPROM and deletion verification method in non-volatile semiconductor storage device

Abstract

A NAND column has memory cell transistors connected in series by a current passage. Word line drive circuits supply a low voltage to a word lines. A potential supply circuit supplies a high potential higher than the low potential, to a semiconductor region in which the memory cell transistors are formed, to delete contents stored in the memory cell transistors. In deletion verification which verifies that the contents stored in the memory cell transistors have been deleted, a read is executed on each of the word lines. In the read, the word line drive circuit provides the selected one of the word lines with a determination potential used to determine whether or not the contents have been deleted, while providing the other non-selected word lines with a read potential higher than the determination potential.

Claims28

Dependent claims

A non-volatile semiconductor storage device comprising:

a NAND column having a plurality of memory cell transistors connected in series by a current passage;
a plurality of word lines connected to gates of the plurality of memory cell transistors in the NAND column;
word line drive circuits which drive the plurality of word lines;
a bit line connected to one end of the NAND column via a selection gate transistor;
a bit line drive circuit which drives the bit line;
a source line connected to the other end of the NAND column via a selection gate transistor;
a source line drive circuit which drives the source line;
and
a potential supply circuit which supplies a potential to a semiconductor region in the NAND column in which the plurality of memory cell transistors are formed;
wherein in deletion verification which verifies that the contents stored in the plurality of memory cell transistors have been deleted, a read is executed on each of the plurality of word lines, and in the read, the word line drive circuit provides the selected one of the plurality of word lines with a determination potential used to determine whether or not the contents have been deleted, while providing the other non-selected word lines with a read potential higher than the determination potential.

7 more elements

A non-volatile semiconductor storage device comprising:

a NAND column having a plurality of memory cell transistors connected in series by a current passage;
a plurality of word lines connected to gates of the plurality of memory cell transistors in the NAND column;
word line drive circuits which drive the plurality of word lines;
a bit line connected to one end of the NAND column via a selection gate transistor;
a bit line drive circuit which drives the bit line;
a source line connected to the other end of the NAND column via a selection gate transistor;
a source line drive circuit which drives the source line;
and
a potential supply circuit which supplies a potential to a semiconductor region in the NAND column in which the plurality of memory cell transistors are formed;
wherein the word line drive circuits supply a low voltage to the plurality of word lines, wherein the potential supply circuit supplies a high potential higher than the low potential, to the semiconductor region in which the plurality of memory cell transistors are formed, to delete contents stored in the plurality of memory cell transistors, and
wherein in deletion verification which verifies that the contents stored in the plurality of memory cell transistors have been deleted, a read is executed on every predetermined number of word lines of the plurality of word lines, the number of the predetermined number of word lines being at least two and smaller than the total number of word lines, and in the read, the word line drive circuit provides the selected ones of the plurality of word lines with a determination potential used to determine whether or not the contents have been deleted, while providing the other non-selected word lines with a read potential higher than the determination potential.

8 more elements

A deletion verification method for a non-volatile semiconductor storage device having a NAND column having a plurality of memory cell transistors connected in series by a current passage and a plurality of word lines connected to gates of the plurality of memory cell transistors in the NAND column, the method comprising:

supplying a low potential to the plurality of word lines, while supplying a high potential higher than the low potential, to a semiconductor region in which the plurality of memory cell transistors are formed, to delete contents stored in the plurality of memory cell transistors;
and
executing a read on every predetermined number of word lines of the plurality of word lines, the number of the predetermined number of word lines being at least two and smaller than the total number of word lines, and in the read, providing the selected ones of the plurality of word lines with a determination potential used to determine whether or not the contents have been deleted, while providing the other non-selected word lines with a read potential higher than the determination potential.

Dependencies are inferred from the claim text.

Non-volatile semiconductor storage device composed of NAND type EEPROM and deletion verification method in non-volatile semiconductor storage device

Life of this patent

Non-volatile semiconductor storage device composed of NAND type EEPROM and deletion verification method in non-volatile semiconductor storage device

Life of this patent

Abstract

Claims28