Semiconductor memory device having row decoder in which high-voltage-applied portion is located adjacent to low-voltage-applied portion

A semiconductor memory device comprising:

• a first, a second, and a third memory cell transistors in each of which information can be electrically rewritten, addresses of the first, second, and third memory cell transistors being consecutive in a row direction;
• a first transfer transistor in which one end of a current passage is connected to a control electrode of the first memory cell transistor and in which a write voltage is applied to the other end;
• a second transfer transistor in which one end of a current passage is connected to a control electrode of the second memory cell transistor and in which a pass voltage lower than the write voltage is applied to the other end;
• a third transfer transistor in which one end of a current passage is connected to a control electrode of the third memory cell transistor and in which a first voltage lower than the pass voltage is applied to the other end;
• a first control section which applies a first on-voltage to make the first transfer transistor conductive, to a gate of the first transfer transistor;
• and
• a second control section which applies a second on-voltage to make the second and third transfer transistors conductive, to gates of the second and third transfer transistors, the second on-voltage being different from the first on-voltage.