NAND type flash EEPROM in which sequential programming process is performed by using different intermediate voltages

A nonvolatile semiconductor memory device comprising:

• a memory cell array having a plurality of memory cell blocks arranged in a column direction and control gate lines provided for each of the plurality of memory cell blocks, each of the memory cell blocks including a plurality of memory cell units arranged in a row S direction and each connected to the control gate lines provided for the memory cell block, each of the plurality of memory cell units including a plurality of electrically data programmable and erasable memory transistors which are arranged in the column direction and whose current paths are serially connected, a first selection gate transistor having a current path connected at one end to one end of a current path of the series-connected memory transistors and connected at the other end to a bit line, and a second selection gate transistor having a current path connected at one end to the other end of the current path of the series-connected memory transistors and connected at the other end to a source line, and each of the control gate lines being commonly connected to control gates of those of the memory transistors which are arranged on a corresponding one of rows in the memory cell units of each of the memory cell blocks,
• a booster circuit which creates and generates program voltage, intermediate voltage and bit line voltage from power supply voltage,
• a row decoder which is supplied with the program voltage and intermediate voltage generated from the booster circuit, selects at least one of the control gate lines and selectively activates first and second selection gate lines respectively connected to gates of the first and second selection gate transistors,
• a bit line control circuit which is supplied with the bit line voltage generated from the booster circuit and performs operations of latching program data and sensing data at the readout time, and
• a column decoder which selects a column of the memory cell units,
• wherein the row decoder applies reference voltage which cuts off the memory transistor to at least one of non-selected control gate line lying near a selected control gate line and applies the intermediate voltage to non-selected control gate lines other than the above non-selected lines when the position of the selected control gate line lies near the bit line and applies the intermediate voltage to the non-selected control gate lines when the position of the selected control gate line is far away from the bit line.

A nonvolatile semiconductor memory device comprising:

• a memory cell array having a plurality of memory cell blocks arranged in a column direction and control gate lines provided for each of the plurality of memory cell blocks, each of the memory cell blocks including a plurality of memory cell units arranged in a row direction and each connected to the control gate lines provided for the memory cell block, each of the plurality of memory cell units including a plurality of electrically data programmable and erasable memory transistors which are arranged in the column direction and whose current paths are serially connected, a first selection gate transistor having a current path connected at one end to one end of a current path of the series-connected memory transistors and connected at the other end to a bit line, and a second selection gate transistor having a current path connected at one end to the other end of the current path of the series-connected memory transistors and connected at the other end to a source line, and each of the control gate lines being commonly connected to control gates of those of the memory transistors which are arranged on a corresponding one of rows in the memory cell units of each of the memory cell blocks,
• a booster circuit which creates and generates program voltage, a plurality of different intermediate voltages and bit line voltage from power supply voltage,
• a row decoder which is supplied with the program voltage and the plurality of different intermediate voltages generated from the booster circuit, selects at least one of the control gate lines and selectively activates first and second selection gate lines respectively connected to gates of the first and second selection gate transistors,
• a bit line control circuit which is supplied with the bit line voltage generated from the booster circuit and performs operations of latching program data and sensing data at the readout time, and
• a column decoder which selects a column of the memory cell units,
• wherein the row decoder applies high voltage among the plurality of different intermediate voltages to non-selected control gate lines which lie on the source line side and applies low voltage among the plurality of different intermediate voltages to non-selected control gate lines which lie on the bit line side at the data programming time.

A nonvolatile semiconductor memory device comprising:

• a memory cell array having a plurality of memory cell blocks arranged in a column direction and n control gate lines provided for each of the plurality of memory cell blocks, each of the memory cell blocks including a plurality of memory cell units arranged in a row direction and each connected to the n control gate lines provided for the memory cell block, each of the plurality of memory cell units including n (n is an integer not smaller than 3) electrically data programmable and erasable memory transistors which are arranged in the column direction and whose current paths are serially connected, a first selection gate transistor having a current path connected at one end to one end of a current path of the series-connected memory transistors and connected at the other end to a bit line, and a second selection gate transistor having a current path connected at one end to the other end of the current path of the series-connected memory transistors and connected at the other end to a source line, and each of the n control gate lines being commonly connected to control gates of those of the memory transistors which are arranged on a corresponding one of rows in the memory cell units of each of the memory cell blocks, and
• a programming circuit configured to program data by holding channel voltage of a selected memory transistor in a selected memory cell unit at a low level when high positive voltage is applied to a selected control gate line and simultaneously to inhibit programming data into all non-selected memory transistors connected to the same selected control gate line by self-boosting channel voltages using capacitive coupling with at least one of the control gate lines,
• wherein a programming process is performed by use of intermediate voltages of m×n types at maximum when sequentially programming data by use of all of the control gate lines in a selected memory cell block by applying first voltage to the selected control gate line, applying m (m is an integer between 2 and (n−1) both inclusive) types of intermediate voltages lower than the first voltage to at least part of non-selected, control gate lines other than the selected control gate line and applying m types of intermediate voltages which are the same as or different from the above m types of intermediate voltages to at least part of non-selected control gate lines other than a next selected control gate line which is different from the former selected control gate line in the selected memory cell block when data is programmed by use of the next selected control gate line.

A nonvolatile semiconductor memory device comprising:

• a memory cell array having a plurality of memory cell blocks arranged in a column direction and n control gate lines provided for each of the plurality of memory cell blocks, each of the memory cell blocks including a plurality of memory cell units arranged in a row direction and each connected to the n control gate lines, each of the plurality of memory cell units including n (n is an integer not smaller than 3) electrically data programmable and erasable memory transistors which are arranged in the column direction and whose current paths are serially connected, a first selection gate transistor having a current path connected at one end to one end of a current path of the series-connected memory transistors and connected at the other end to a bit line, and a second selection gate transistor having a current path connected at one end to the other end of the current path of the series-connected memory transistors and connected at the other end to a source line, and each of the n control gate lines being commonly connected to control gates of those of the memory transistors which are arranged on a corresponding one of rows in the memory cell units of each of the memory cell blocks, and
• a programming circuit configured to program data by holding channel voltage of a selected memory transistor in a selected memory cell unit at a low level when high positive voltage is applied to a selected control gate line and simultaneously to inhibit programming data into all non-selected memory transistors connected to the same selected control gate line by self-boosting channel voltages using capacitive coupling with at least one of the control gate lines,
• wherein first voltage is applied to the selected control gate line, second voltage lower than the first voltage is applied to at least part of non-selected control gate lines on the bit line side with respect to the selected control gate line and third voltage lower than the first voltage is applied to at least part of non-selected control gate lines on the source line side with respect to the selected control gate line when the selected control gate line lies in one of first to ith (i is an integer between 1 and n both inclusive) positions from the bit line side and the first voltage is applied to the selected control gate line, fourth voltage lower than the first voltage is applied to at least part of non-selected control gate lines on the bit line side with respect to the selected control gate line and fifth voltage lower than the first voltage is applied to at least part of non-selected control gate lines on the source line side with respect to the selected control gate line when the selected control gate line lies in one of (i+1)th to nth positions from the bit line side.

A nonvolatile semiconductor memory device comprising:

• a memory cell array having a plurality of memory cell blocks arranged in a column direction and n control gate lines provided for each of the plurality of memory cell blocks, each of the memory cell blocks including a plurality of memory cell units arranged in a row direction and each connected to the n control gate lines, each of the plurality of memory cell units including n (n is an integer not smaller than 3) electrically data programmable and erasable memory transistors which are arranged in the column direction and whose current paths are serially connected, a first selection gate transistor having a current path connected at one end to one end of a current path of the series-connected memory transistors and connected at the other end to a bit line, and a second selection gate transistor having a current path connected at one end to the other end of the current path of the series-connected memory transistors and connected at the other end to a source line, and each of the n control gate lines being commonly connected to control gates of those of the memory transistors which are arranged on a corresponding one of rows in the memory cell units of each of the memory cell blocks, and
• a programming circuit configured to program data by holding channel voltage of a selected memory transistor in a selected memory cell unit at a low level when high positive voltage is applied to a selected control gate line and simultaneously to inhibit programming data into all non-selected memory transistors connected to the same selected control gate line by self-boosting channel voltages using capacitive coupling with at least one of the control gate lines,
• wherein if the selected control gate line lies in a kth (k is an integer between 1 and n both inclusive) position from the bit line side, a programming process is performed by use of Vpass(k) of n types at maximum when data is sequentially programmed via all of the control gate lines in a selected memory cell block by applying first voltage to the selected control gate line and applying Vpass(k) lower than the first voltage and depending on k to at least part of non-selected control gate lines.

A nonvolatile semiconductor memory device comprising:

• a memory cell array having a plurality of memory cell blocks arranged in a column direction and n control gate lines provided for each of the plurality of memory cell blocks, each of the memory cell blocks including a plurality of memory cell units arranged in a row direction and each connected to the n control gate lines, each of the plurality of memory cell units including n (n is an integer not smaller than 3) electrically data programmable and erasable memory transistors which are arranged in the column direction and whose current paths are serially connected, a-first selection gate transistor having a current path connected at one end to one end of a current path of the series-connected memory transistors and connected at the other end to a bit line, and a second selection gate transistor having a current path connected at one end to the other end of the current path of the series-connected memory transistors and connected at the other end to a source line, and each of the n control gate lines being commonly connected to control gates of those of the memory transistors which are arranged on a corresponding one of rows in the memory cell units of each of the memory cell blocks, and
• a programming circuit configured to program data by holding channel voltage of a selected memory transistor in a selected memory cell unit at a low level when high positive voltage is applied to a selected control gate line and simultaneously to inhibit programming data into all non-selected memory transistors connected to the same selected control gate line by self-boosting channel voltages using capacitive coupling with at least one of the control gate lines,
• wherein first voltage is applied to the selected control gate line and sixth voltage lower than the first voltage is applied to at least part of non-selected control gate lines when the selected control gate line lies in one of first to ith (i is an integer between 1 and n both inclusive) positions from the bit line side and seventh voltage lower than the first voltage is applied to at least part of non-selected control gate lines when the selected control gate line lies in one of (i+1)th to nth positions from the bit line side.

A nonvolatile semiconductor memory device comprising:

• a memory cell array having a plurality of memory cell blocks arranged in a column direction and n control gate lines provided for each of the plurality of memory cell blocks, each of the memory cell blocks including a plurality of memory cell units arranged in a row direction and each connected to the n control gate lines, each of the plurality of memory cell units including n (n is an integer not smaller than 3) electrically data programmable and erasable memory transistors which are arranged in the column direction and whose current paths are serially connected, a first selection gate transistor having a current path connected at one end to one end of a current path of the series-connected memory transistors and connected at the other end to a bit line, and a second selection gate transistor having a current path connected at one end to the other end of the current path of the series-connected memory transistors and connected at the other end to a source line, and each of the n control gate lines being commonly connected to control gates of those of the memory transistors which are arranged on a corresponding one of rows in the memory cell units of each of the memory cell blocks, and
• a programming circuit configured to program data by holding channel voltage of a selected memory transistor in a selected memory cell unit at a low level when high positive voltage is applied to a selected control gate line and simultaneously to inhibit programming data into all non-selected memory transistors connected to the same selected control gate line by self-boosting channel voltages using capacitive coupling with at least one of the control gate lines,
• wherein first voltage is applied to the selected control gate line and m (m is an integer between 2 and (n−1) both inclusive) types of intermediate voltages which are lower than the first voltage are applied to at least part of non-selected control gate lines which are different from the selected control gate line.

A nonvolatile semiconductor memory device comprising:

• a memory cell array having a plurality of memory cell blocks arranged in a column direction and n control gate lines provided for each of the plurality of memory cell blocks, each of the memory cell blocks including a plurality of memory cell units arranged in a row direction and each connected to the n control gate lines, each of the plurality of memory cell units including n (n is an integer not smaller than 3) electrically data programmable and erasable memory transistors which are arranged in the column direction and whose current paths are serially connected, a first selection gate transistor having a current path connected at one end to one end of a current path of the series-connected memory transistors and connected at the other end to a bit line, and a second selection gate transistor having a current path connected at one end to the other end of the current path of the series-connected memory transistors and connected at the other end to a source line, and each of the n control gate lines being commonly connected to control gates of those of the memory transistors which are arranged on a corresponding one of rows in the memory cell units of each of the memory cell blocks, and
• a programming circuit configured to program data by holding channel voltage of a selected memory transistor in a selected memory cell unit at a low level when high positive voltage is applied to a selected control gate line and simultaneously to inhibit programming data into all non-selected memory transistors connected to the same selected control gate line by self-boosting channel voltages using capacitive coupling with at least one of the control gate lines,
• wherein a programming system is used in which a memory transistor is cut off by applying first voltage to the selected control gate line and applying second voltage lower than the first voltage to part of non-selected control gate lines to turn off non-selected memory transistors connected to the above non-selected control gate lines and to limit a self-boosting channel region when the selected control gate line is a kth control gate line from the bit line side and the number Nlow(k) (Nlow(k) is an integer not smaller than 0) of control gate lines to which the second voltage is applied is changed depending on k.