Storage array such as a SRAM with reduced power requirements

A static random access memory (SRAM) comprising:

• an array of SRAM cells, arranged in rows and columns;
• a word line decoder selecting a row of cells, ones of said selected row of cells being accessed bits;
• a bit decoder selecting columns, cells in selected columns being said accessed bits;
• a sense amplifier in each bit path receiving a differential signal from a corresponding one of said accessed bits and providing a data output responsive to said differential signal;
• and
• a read/write-select in said each bit path selectively blocking cell writes unless cell contents are being changed for a corresponding bit.

A CMOS static random access memory (SRAM) comprising:

• an array of SRAM cells arranged in rows and columns;
• a power supply select at each row selectively increasing cell supply voltage to said each row;
• a word line decoder selecting a row of cells, said selected row of cells being increased to a supply voltage and cells in remaining rows being provided a reduced supply voltage, ones of said selected row of cells being accessed;
• a bit decoder selecting columns, cells in selected columns being said accessed bits;
• a sense amplifier in each bit path receiving a differential signal from a corresponding one of said accessed bits and providing a data output responsive to said differential signal;
• and
• a read/write-select in said each bit path selectively blocking cell writes unless cell contents are being changed for a corresponding bit, wherein leakage is substantially lower in said remaining rows than in said selected row.