Ferroelectric memory

A ferroelectric, non-volatile memory comprising a pair of complementary bit lines, a drive line located between and parallel to said complementary bit lines, a word line perpendicular to said bit lines and drive line, and a memory cell comprising:

• a first ferroelectric capacitor, a second ferroelectric capacitor, a first transistor, a second transistor, and a drive line transistor;
• wherein said first transistor is connected between said first capacitor and one of said complementary bit lines, said second transistor is connected between said second capacitor and the other of said complementary bit lines, and said drive line transistor is connected between at least one of said capacitors and said drive line.

A ferroelectric, non-volatile memory having a plurality of memory cells arranged in rows and columns, each column comprising a bit line coupled to memory cells along the column, each row comprising a word line coupled to cells along the row, said memory also including a plurality of drive lines distinct from said bit and word lines, each said memory cell coupled to a corresponding drive line, each said memory cell comprising a ferroelectric element, the polarization of said ferroelectric element corresponding to the data stored therein, said memory also including a signal generator providing a read signal, the improvement wherein said memory further comprises a bit line driver circuit responsive to said read signal for driving said bit line to a voltage of no more than one volt.

A ferroelectric, non-volatile memory of the type having a plurality of memory cells arranged in rows and columns, each column comprising a bit line coupled to memory cells along the column, each row comprising a word line coupled to cells along the row, said memory also including a plurality of drive lines distinct from said bit and word lines, each said memory cell coupled to a corresponding drive line, each said memory cell comprising a ferroelectric element, the polarization of said ferroelectric element corresponding to the data stored therein, said memory also including a signal generator providing a read signal, the improvement wherein two of said bit lines are complementary dummy bit lines and one of said bit lines is not a dummy bit line;

• said memory further comprises:
• a sense amplifier having a first bit line input connectable to said bit line that is not a dummy bit line, a second bit line input connectable to a first one of said dummy bit lines, and a third bit line input connectable to a second one of said dummy bit lines.

A ferroelectric, non-volatile memory having a plurality of memory cells arranged in rows and columns, each column comprising a bit line coupled to memory cells along the column, each row comprising a word line coupled to cells along the row, said memory also including a plurality of drive lines distinct from said bit and word lines, each said memory cell coupled to a corresponding drive line, each said memory cell comprising a ferroelectric element, the polarization of said ferroelectric element corresponding to the data stored therein, the improvement wherein said bit lines are top level bit lines and there are a plurality of said memory cells divided into a first group and a second group, said memory further including a first group select transistor having a gate, a second group select transistor having a gate, a first group select line, a second group select line, a first second level bit line, and a second second level bit line, and wherein said first group select transistor is connected between said top level bit line and said first second level bit line, said second group select transistor is connected between said top level bit line and said second second level bit line, said first group select line is connected to said gate of said first group select transistor, and said second group select line is connected to said gate of said second group select transistor.

A method of operating a ferroelectric, non-volatile memory comprising a plurality of memory cells, each said memory cell including a memory cell ferroelectric element, said method comprising:

• electrically isolating each of said memory cell ferroelectric elements from all other said memory cell ferroelectric elements.

A method of operating a ferroelectric, non-volatile memory of the type having a plurality of memory cells arranged in rows and columns, each column comprising a bit line pair coupled to memory cells along the column, each row comprising a word line coupled to cells along the row, said memory also including a plurality of drive lines distinct from said bit and word lines, each said memory cell coupled to a corresponding drive line, each said memory cell comprising a pair of ferroelectric memory elements, the polarization of each of said ferroelectric memory elements corresponding to the data stored therein;

• said method comprising:
• electrically isolating each of said ferroelectric memory element pairs from all other ferroelectric memory element pairs.

A method of reading a ferroelectric, non-volatile memory of the type having at least twenty-five memory cells arranged in rows and columns, each column comprising a bit line coupled to memory cells along the column, each row comprising a word line coupled to cells along the row, said memory also including a plurality of drive lines distinct from said bit and word lines, each said memory cell coupled to a corresponding drive line, each said memory cell comprising a ferroelectric memory element, the polarization of said ferroelectric memory element corresponding to the data stored therein, said method comprising:

• reading one of said memory cells connected to a selected drive line;
• and electrically connecting no more than four of said ferroelectric memory elements to said selected drive lines during said step of reading.

A method of reading a ferroelectric, non-volatile memory of the type having a plurality of memory cells arranged in rows and columns, each column comprising a bit line coupled to memory cells along the column, each row comprising a word line coupled to cells along the row, said memory also including a plurality of drive lines distinct from said bit and word lines, each said memory cell coupled to a corresponding drive line, each said memory cell comprising a ferroelectric memory element, the capacitance state of said ferroelectric memory element corresponding to the data stored therein, said method comprising:

• electrically connecting a selected memory cell to a selected bit line;
• and
• providing a data output signal corresponding to said capacitance state of said ferroelectric memory element.

A method of reading a ferroelectric, non-volatile memory of the type having a plurality of memory cells arranged in rows and columns, each column comprising a bit line coupled to memory cells along the column, each row comprising a word line coupled to cells along the row, said memory also including a plurality of drive lines distinct from said bit and word lines, each said memory cell coupled to a corresponding drive line, each said memory cell comprising a ferroelectric capacitor, the polarization of said ferroelectric memory element corresponding to the data stored therein, said method comprising:

• selecting one of said ferroelectric memory cells;
• and
• reading the capacitor in said selected memory cell without changing the ferroelectric polarization state of said capacitor.

A method of operating a ferroelectric, non-volatile memory of the type having a plurality of memory cells arranged in rows and columns, each column comprising a bit line coupled to memory cells along the column, said bit lines including a first dummy bit line connected to a first dummy memory cell, each row comprising a word line coupled to cells along the row, said memory also including a plurality of drive lines distinct from said bit and word lines, each said memory cell coupled to a corresponding drive line, each said memory cell comprising a ferroelectric memory element, the polarization of said ferroelectric memory element corresponding to the data stored therein;

• said method comprising:
• writing a first logic state to said first dummy memory cell in a first memory cycle and writing a second logic state to said first dummy memory cell in a second memory cycle.

A method of selecting a memory cell in a ferroelectric, non-volatile memory having a plurality of memory arrays, each said memory array having a plurality of memory cells arranged in rows and columns:

• selecting one of said plurality of arrays;
• and
• selecting a memory cell in said selected array.

A method of writing to a ferroelectric, non-volatile memory, said method comprising:

• selecting a single memory cell used in complementary mode in said memory;
• and writing data to said selected memory cell without electrically connecting it to any non-selected memory cell in said memory.

A method of writing to a ferroelectric, non-volatile memory, said method comprising:

• selecting a single memory cell in said memory;
• and writing data to said selected memory cell without electrically connecting it to any non-selected memory cell in said memory.

A method of reading a ferroelectric, non-volatile memory, said method comprising:

• selecting a single memory cell used in complementary mode in said memory;
• and reading said memory cell without electrically connecting to any non-selected memory cell in said memory.

A method of reading a ferroelectric, non-volatile memory, said method comprising:

• selecting a single memory cell in said memory;
• and writing data to said selected memory cell without electrically connecting it to any non-selected memory cell in said memory.