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US 2004/0105293 A1Published application
Reducing effects of noise coupling in integrated circuits with memory arrays
AssigneesInfineon Technologies AG, Kabushiki Kaisha Toshiba
InventorsMichael Jacob, Thomas Roehr, Norbert Rehm, Daisaburo Takashima
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Abstract
A method for reducing noise coupling in a memory array is disclosed. The memory array includes a plurality memory cells interconnected by wordlines, bitlines, and platelines. The memory cells are arranged in columns having first and second bitlines coupled to a sense amplifier. During a memory access, at least adjacent bitlines pairs are not activated. The selected bitline pair or pairs are provided with a plateline pulse.
Claims43
a method of operating memory array with reduced noise coupling comprising:
- providing a memory array having a plurality memory cells interconnected by wordlines, bitlines, and platelines, the memory cells of the array are arranged in a plurality of columns, a column comprises a bitline pair having first and second bitlines coupled to a sense amplifier;
- performing a memory access to the array, the access selects one of the columns of memory cells;
- and
- providing a plateline pulse to the selected column.
1 more element
Dependencies are inferred from the claim text.