Memory system and data transmission method

A memory system having a plurality of modules each mounted with a plurality of memory circuits, and a controller for controlling the memory circuits of said plurality of modules, wherein each of said modules is provided with at least one buffer, and the buffer of each module is connected to the buffer of another module and/or said controller via data wiring for data transmission.

A memory system having a module mounted with a buffer and a memory circuit connected to said buffer, and a memory controller connected to said buffer on said module, wherein a transmission speed between said memory controller and said buffer is higher than a transmission speed between said buffer on said module and said memory circuit connected to said buffer.

A data transmission method for transmitting/receiving data bidirectionally between a first and a second device, said first device receiving data according to first internal clocks, and said second device receiving data according to second internal clocks, wherein a first and a second data phase signal are continuously transmitted bidirectionally on the same wiring between said first and second devices at timing that avoids collision therebetween, said first device refers to timing of said first data phase signal to thereby transmit data to said second device, while said second device refers to timing of said second data phase signal to thereby transit data to said first device.

A data transmission system for transmitting/receiving data between a first and a second device, wherein a transmission side of said first and second devices has means for transmitting, upon transmission of said data, a data phase signal representing a predetermined phase of said data continuously irrespective of transmission of said data, and a reception side of said first and second devices has means for reproducing internal clocks of said reception side based on said data phase signal and receiving said data according to the reproduced internal clocks.

A data transmission system for transmitting/receiving data bidirectionally between a first and a second device, wherein each of said first and second devices has transmission means for transmitting, upon transmission of said data, a data phase signal representing a predetermined phase of said data continuously irrespective of transmission of said data, and transmitting said data based on said data phase signal, and reception means for reproducing data reception internal clocks based on said data phase signal and receiving said data according to the reproduced internal clocks.

A memory module having a plurality of memory circuits and a buffer, wherein a command/address signal is transmitted from said buffer to said plurality of memory circuits, and data signals following said command/address signal are transmitted/received between said buffer and said plurality of memory circuits, wherein at least one of said plurality of memory circuits and said buffer has skew absorbing means for absorbing timing skews that are caused to occur between said command/address signal and said data signals in dependency on mounting positions of said memory circuits.

A memory module having a plurality of memory circuits and a buffer, wherein a command/address signal is transmitted from said buffer to said plurality of memory circuits, and data signals following said command/address signal are transmitted/received between said buffer and said plurality of memory circuits, wherein said data signals are transmitted/received between said plurality of memory circuits and said buffer synchronously with data phase signals transmitted onto the same signal line alternately from said memory circuits and said buffer, and said buffer has means for outputting a control signal for defining a transmission time of said data phase signal in each of said memory circuits and said buffer.

A memory system having a plurality of memory circuits and a control circuit for controlling said plurality of memory circuits according to main clocks, wherein said plurality of memory circuits and said control circuit are connected via first wiring for transmitting/receiving data signals, and second wiring having a length different from that of said first wiring, characterized in that said control circuit attains a clock signal obtained by n-dividing (n is a positive integer equal to or greater than 2) said main clocks in frequency, outputs a command/address signal to said plurality of memory circuits via said second wiring while matching said command/address signal with said n-divided clock signal, and outputs via said first wiring a data phase signal (DPS) having a predetermined frequency relationship with said n-divided clock signal and representing a phase of said data signal, and said plurality of memory circuits each absorb a timing skew caused by a difference in wiring length between said first and second wirings, using said data phase signal.