Content addressable memory with cascaded array
AssigneeNetLogic Microsystems, Inc.
InventorSandeep Khanna
Life of this patent
Estimating the term…
Abstract
A content addressable memory (CAM) device having a cascaded CAM array. The cascaded CAM array includes a first array of CAM cells and a second array of CAM cells. A first plurality of compare signal lines is coupled to the first array CAM cells and a second plurality of compare signal lines coupled to the second array of CAM cells. A plurality of storage elements have inputs coupled to the first plurality of compare signal lines and outputs coupled to the second plurality of compare signal lines.
Claims36
A content addressable memory (CAM) device comprising:
- a CAM array having a first array of CAM cells and a second array of CAM cells;
- a first plurality of compare signal lines coupled to the first array CAM cells;
- a second plurality of compare signal lines coupled to the second array of CAM cells;
- and
- a plurality of storage elements having inputs coupled to the first plurality of compare signal lines and outputs coupled to the second plurality of compare signal lines.
A method of operation within a content addressable memory (CAM) device, the method comprising:
- outputting a first comparand value onto a first plurality of compare signal lines for comparison with contents of a first array of CAM cells;
- storing the first comparand value in a storage circuit coupled to the first plurality of compare signal lines;
- and
- outputting the first comparand value from the storage circuit to a second plurality of compare signal lines for comparison with contents of a second array of CAM cells.
A content addressable memory (CAM) device comprising:
- a first array of CAM cells;
- a first plurality of compare signal lines coupled to the first array of CAM cells;
- a second array of CAM cells;
- a second plurality of compare signal lines coupled to the second array of CAM cells;
- and
- means for outputting a first comparand value onto the first plurality of compare signal lines for comparison with contents of the first array of CAM cells;
- and
- means for receiving the first comparand value from the first plurality of compare lines, storing the first comparand value, and outputting the first comparand value onto the second plurality of compare signal lines for comparison with contents of the second array of CAM cells.
Dependencies are inferred from the claim text.