Electrostatic discharge protection circuit of non-gated diode and fabrication method thereof

An ESD protection circuit of a non-gated diode, coupled between an output pad and a pre-driver, comprising:

• a high-voltage supply rail and a low-voltage supply rail, coupled to the pre-driver;
• a first diode, with an anode coupled to the high-voltage supply rail and a cathode coupled to a node;
• a second diode, with a cathode coupled to the low-voltage supply rail and an anode coupled to the node;
• a first diode series, having a plurality of serially connected diodes, wherein an anode thereof is coupled to the high-voltage supply rail and a cathode thereof is coupled to the node;
• a second diode series, having a plurality of serially connected diodes, wherein a cathode thereof is coupled to the low-voltage supply rail and an anode thereof is coupled to the node;
• and
• a first type MOS transistor, with a source region coupled to the high-voltage supply rail, a drain region coupled to the node and a gate coupled to the pre-driver;
• and
• a second type MOS transistor, with a source region coupled to the low-voltage supply rail, a drain region coupled to the node and a gate coupled to the gate of the first type MOS transistor.

An ESD protection circuit of a non-gated diode, coupled between an input pad and an internal circuit, comprising:

• a high-voltage supply rail and a low-voltage supply rail, coupled to the internal circuit;
• a first diode and a second diode serially connected together, wherein an anode of the first diode is coupled to a node, and a cathode of the second diode is coupled to the high-voltage supply rail;
• a third diode and a fourth diode serially connected together, wherein an anode of the third diode is coupled to the low-voltage supply rail a node, and a cathode of the fourth diode is coupled to the node;
• and
• an ESD clamp circuit, coupled between the high- and low-voltage supply rails.

A non-gated diode structure in a CMOS process, comprising:

• a substrate having a well region therein;
• a pair of blocking isolation structures in the substrate;
• a first type doped region located in the well region and between the blocking isolation structures;
• and
• a pair of second type doped regions located in the well region and respectively adjacent to the blocking isolation structure, wherein each second type doped region is separated from the first type doped region by the well.

A method of forming a non-gate diode in a CMOS process, comprising:

• providing a substrate having a well region therein;
• forming a pair of blocking isolation structures in the substrate;
• forming a first type doped region located in the well region and between the blocking isolation structures;
• and
• forming a pair of second type doped regions located in the well region and respectively adjacent to the blocking isolation structure, wherein each second type doped region is separated from the first type doped region by the well.