High dynamic linearity current-mode digital-to-analog converter architecture
AssigneeEngim, Inc.
InventorAlexander Bugeja
Life of this patent
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Abstract
The present invention dramatically reduces dynamic mismatches between the different current segments of a segmented current-mode DAC. By providing substantially the same local architecture for each of the individual current segments, parasitic effects of any physical realization can be controlled. In one embodiment, the most-significant-bit (MSB) current segments and the least-significant-bit (LSB) current segments each have the same number of multiple internal current branches. In the MSB segments, the multiple internal current branches are combined at a source node; whereas, in the LSB segment, a portion of the segment current is dumped, or wasted, through at least some of the internal current branches.
Claims35
A segmented, current-mode Digital-to-Analog Converter (DAC) comprising:
- a summing node;
- a dump node;
- a control input;
- a Most Significant Bit (MSB) current leg coupled to the summing node, the MSB current leg conducting a first current relative to the summing node in response to the control input;
- and
- a Least Significant Bit (LSB) current leg coupled to the summing node, the LSB current leg conducting a second current relative to the summing node in response to the control input and conducting current relative to the dump node.
A digital-to-analog converting method for generating a linear, high-speed analog output signal comprising:
- receiving a control input;
- conducting in a Most Significant Bit (MSB) current leg, a first current relative to a summing node in response to receiving the control input;
- conducting in a Least Significant Bit (LSB) current leg, a second current relative to the summing node in response to receiving the control input;
- and
- conducting in the LSB current leg, a current relative to a dump node.
A digital-to-analog converter comprising:
- means for receiving a control input;
- means for conducting, in response to the received control input, a first current in a Most Significant Bit (MSB) current leg;
- means for conducting, in response to the received control input, a second current in a Least Significant Bit (LSB) current leg;
- and
- means for dumping a portion of the second current;
- and
- means for combining the first current, the second current, and the dump current.
Dependencies are inferred from the claim text.