Wide range multi-phase delay-locked loop
AssigneeSilicon Image, Inc.
InventorsYongsam Moon, Gijung Ahn, Deog-Kyoon Jeong
Life of this patent
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Abstract
A delay locked loop apparatus includes a first delay element to receive a reference signal, to delay the reference signal by a delay time, and to output a first delayed signal. A second delay element is used to receive the first delayed signal, to delay the first signal delayed signal by the delay time, and to output a second delayed signal. Also included is a harmonic lock prevention circuit to receive the reference signal, the first delayed signal, and the second delayed signal, and to adjust the delay time so that a period of each delayed signal is within a predetermined range.
Claims7
A delay locked loop apparatus comprising:
- a first delay element to receive a reference signal, to delay the reference signal by a delay time, and to output a first delayed signal;
- a second delay element to receive the first delayed signal, to delay the first signal delayed signal by the delay time, and to output a second delayed signal;
- and
- a harmonic lock prevention circuit to receive the reference signal, the first delayed signal, and the second delayed signal, and to adjust the delay time so that a period of each delayed signal is within a predetermined range.
Dependencies are inferred from the claim text.