Cascoded power amplifier, particularly for use in radio frequency
AssigneeSTMicroelectronics S.r.l.
InventorsBruno Murari, Alessandro Moscatelli, Lorenzo Labate
Life of this patent
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Abstract
A power amplifier comprising at least a load element and at least an active element inserted, in series to each other, between a first and a second voltage reference is described. Advantageously, according to an embodiment of the invention, the load element comprises a DMOS transistor.
Claims24
A power amplifier of a type comprising at least a load element and at least an active element inserted, in series to each other, between a first and a second voltage reference, wherein said load element includes a DMOS transistor.
An apparatus, comprising:
- a load element having a first terminal coupled to a first voltage reference, a second terminal coupled to receive a first control voltage, and a third terminal;
- and
- an active element in cascode configuration and having a first terminal coupled to the third terminal of the load element, a second terminal coupled to receive a second control voltage, and a third terminal coupled to a second voltage reference,
- wherein the second control voltage is set and integration limits of the load element are fixed to allow the active element to operate in a saturation area to provide high cutoff frequency and a high transconductance value and in a linear area to prove low activation resistance.
A power amplifier usable in radio frequency applications, the power amplifier comprising:
- first and second voltage references;
- a transistor load element having a first terminal coupled to the first voltage reference, a second terminal coupled to receive a first control voltage, and a third terminal;
- and
- an active element in cascode configuration and having a first terminal coupled to the third terminal of the transistor load element, a second terminal coupled to a second control voltage, and a third terminal coupled to the second voltage reference, wherein the transistor load element is sized and biased and the second control voltage is set to allow the active element to operate in a saturation area to provide high cutoff frequency and a high transconductance value and in a linear area to prove low activation resistance.
A method, comprising:
- sizing and biasing a transistor load element to allow an active element to operate in a saturation area;
- receiving a first control voltage at a control terminal of the load element to allow the active element to operate in the saturation area;
- setting a second control voltage at a control terminal of the active element to allow the active element to operate in the saturation area;
- and
- obtaining high cutoff frequencies and high transconductance values in the saturation area, and obtaining low on-state resistance values in a linear area of operation.
An apparatus, comprising:
- a means for sizing and biasing a transistor load element to allow an active element to operate in a saturation area;
- a means for receiving a first control voltage at a control terminal of the load element to allow the active element to operate in the saturation area;
- a means for setting a second control voltage at a control terminal of the active element to allow the active element to operate in the saturation area;
- and
- a means for obtaining high cutoff frequencies and high transconductance values in the saturation area, and obtaining low on-state resistance values in a linear area of operation.
Dependencies are inferred from the claim text.