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US 2004/0104756 A1Published application
Voltage level shifter circuit having high speed and low switching power
OwnerJames E. Payneinventor
Life of this patent
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Abstract
A voltage level shifter comprises a plurality of PMOS transistors coupled in series with NMOS transistors to form a plurality of pull-down inverters. When the second voltage level is enabled to connect, the pull-down inverters pull down faster than the pull-down NMOS transistors alone, and thus, the pull-up PMOS transistors pull up immediately to connect the first voltage level to the second voltage level. Thus, the PMOS transistors added to form pull-down inverters improve the switching time and eliminate the kinks in the output voltage.
Claims6
A voltage level shifter circuit, comprising:
- (a) a plurality of PMOS pull-up transistors, each having a drain terminal coupled to a first voltage level;
- (b) a plurality of pull-down inverter means for improving a switching time of the voltage level shifter, wherein each pull-down inverter means is coupled in series with each of the plurality of pull-up transistors;
- (c) an output buffer circuit coupled to the plurality of pull-down inverter means;
- and
- (d) a plurality of input inverters coupled to the plurality of pull-down inverter means and to a second voltage level.
2 more elements
A voltage level shifter circuit comprising:
- (a) a first PMOS transistor and a second PMOS transistor coupled to a first voltage level, each having a drain, a gate, a source, and a body;
- (b) a third PMOS transistor and a fourth PMOS transistor each having a drain, a gate, a source, and a body, wherein the body of the third transistor being coupled to the body of the first PMOS transistor and to the first voltage level, the body of the fourth PMOS transistor being coupled to the body of the second PMOS transistor and to the first voltage level, the drain of the third PMOS transistor being coupled to the source of the first PMOS transistor, the drain of the fourth PMOS transistor being coupled to the source of the second PMOS transistor;
- (c) the first NMOS transistor and a second NMOS transistor, each having a gate, a drain, and a source, wherein the drain of the first NMOS transistor being coupled to the source of the third PMOS transistor and to the gate of the second PMOS transistor, the gate of the first NMOS transistor coupled to the gate of the third PMOS transistor, the drain of the second NMOS transistor being coupled to the source of the fourth PMOS transistor, the gate of the second NMOS transistor coupled to the gate of the fourth PMOS transistor;
- (d) a first inverter and a second inverter, each having an input terminal and an output terminal, wherein the input terminal of the first inverter being coupled to a second voltage level, the output of the first inverter being coupled to the gate of the first NMOS transistor and to the input of the second inverter, the output of the second inverter coupled to the gate of the second NMOS transistor;
- (e) a first output inverter and a second output inverter, wherein the first output inverter further comprising a fifth PMOS transistor and a third NMOS transistor, the second output inverter having a sixth PMOS transistor and a fourth NMOS transistor, each transistor having a drain, a gate, and a source;
- the gates of the fifth PMOS transistor and the third NMOS transistor coupled together and to the gate of the first PMOS transistor, the drain of the fifth PMOS transistor coupled to the first voltage level, the source of the fifth PMOS transistor coupled to the drain of the third NMOS transistor, the source of the third transistor coupled to the electrical ground;
- the gates of the sixth PMOS transistor and the fourth NMOS transistor coupled together and to the source of the fifth PMOS transistor, the drain of the sixth PMOS transistor coupled to the first voltage level, the source of the sixth PMOS transistor coupled to the drain of the fourth NMOS transistor, and the source of the fourth NMOS transistor coupled to the electrical ground.
4 more elements
Dependencies are inferred from the claim text.