Semiconductor device capable of accurately producing internal multi-phase clock signal

A semiconductor device comprising:

• first internal clock generation circuitry for producing a first internal clock signal synchronized with a basic clock signal, said first internal clock generation circuitry including a first phase difference detecting circuit for detecting a phase difference between said basic clock signal and said first internal clock signal to produce a first control signal in accordance with the phase difference, and a first clock generating circuit having an operation speed thereof determined in accordance with the first control signal outputted by said phase difference detecting circuit and operating in accordance with the operation speed to produce a clock signal corresponding to said basic clock signal as said first internal clock signal;
• and
• second internal clock generation circuitry for producing a second internal clock signal synchronized with a synchronization target signal, said second internal clock generation circuitry including a second phase difference detecting circuit for detecting a phase difference between said synchronization target signal and said second internal clock signal to produce a phase error signal in accordance with the phase difference, a control circuit for producing a second control signal in accordance with at least a signal corresponding to said first control signal and said phase error signal, and a second clock generating circuit having an operation speed thereof determined in accordance with the second control signal outputted by said control circuit and operating in accordance with the operation speed to produce a signal corresponding to said synchronization target signal as said second internal clock signal.