System and method for expanding a pulse width

A circuit for extending a pulse width comprising:

• a) a capacitor charged by a first control transistor;
• b) a shift signal means in electrical connection with the capacitor, the shift signal means producing a pulse-type shift signal in response to an input signal, the shift signal means having a second control transistor, wherein a gate of the second control transistor is controlled by a charging level of the capacitor, the second control transistor adding a first delay to the input signal's falling edge to produce the shift signal, the first delay added to the shift signal until a pulse width of the shift signal is zero;
• and
• c) an output signal means in electrical connection with the capacitor, the output signal means producing a pulse-type output signal in response to the input signal, the output signal means having a third control transistor, wherein a gate of the third control transistor is controlled by the charging level of the capacitor, the third control transistor adding a second delay to an output signal's falling edge, wherein the second delay is equal to the first delay such that the output signal's pulse width is expanded while the shift signal's pulse width is decreased.

A circuit for extending a pulse width comprising:

• a) a capacitor in electrical connection with a first control transistor which charges the capacitor;
• b) a shift signal block having a second control transistor in electrical connection with:
• i) the capacitor which applies charge to a gate of the second control transistor, whereby a delay is added to a falling edge of a shift signal;
• and
• ii) the first control transistor, whereby a pulse of the shift signal activates the first control transistor;
• and
• c) an output block having a third control transistor in electrical connection with the capacitor which applies charge to gate of the third control transistor, whereby a delay is added to a falling edge of an output signal.

A method of extending a periodic pulse comprising:

• a) receiving a low state input pulse at a shift signal block generating a shift signal and an output block generating an output signal;
• b) charging a capacitor with a transistor activated by the shift signal;
• c) applying charge from the capacitor to both the shift signal block and the output block, wherein a delay in a falling edge of the shift signal and output signal is generated;
• and
• d) repeating steps a-c at each cycle, wherein the capacitor is no longer charged when there is no pulse on the shift signal.