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US 2004/0104750 A1Published application
Phase locked loop (PLL) for integrated circuits
AssigneeSTMicroelectronics Pvt. Ltd.
InventorsRajesh Bajaj, Nipun Padha
Life of this patent
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Abstract
An improved Phase Locked Loop (PLL) for digital integrated circuits. A characteristic of this PLL is that the Voltage Controlled Oscillator (VCO) output is fed to the phase and frequency detector (PFD) input through a clock-tree replica providing a delay equal to the routed clock tree.
Claims22
An improved Phase Locked Loop (PLL) for a digital integrated circuit comprising:
- a routed clock tree connected between said VCO and a leaf cell and a frequency divider in the feedback path to the PFD input, characterized in that,
- the VCO output is fedback to the PFD input through a clock tree replica providing a delay equal to the routed clock tree.
A method for providing an improved Phase Locked Loop (PLL) for a digital integrated circuit comprising the steps of:
- providing a Phase and Frequency Detector (PFD) for comparing the input clock and the generated clock,
- connecting a Voltage Controlled Oscillator (VCO) at the output of the PFD for producing a clock output and a frequency divider in the feedback path to the PFD input, characterized in that the VCO output is fedback to the PFD input through a clock tree replica providing a delay equal to the routed clock tree.
A phase-locked loop, comprising:
- a phase detector operable to generate an error signal that is related to a phase difference between a reference signal and a delayed output signal;
- a signal-controlled oscillator coupled to the phase detector and operable to generate an output signal having a frequency that is related to the error signal;
- and
- a feedback circuit coupled to the phase detector and to the oscillator and operable to generate the delayed output signal by delaying the output signal substantially by a same time that the output signal is delayed between the oscillator and a remote circuit.
1 more element
An integrated circuit, comprising:
- a circuit;
- a delay path having an output node coupled to the circuit, an input node, and a signal delay;
- and
- a phase-locked loop having an output node coupled to the input node of the delay path, the phase-locked loop comprising,
- a phase detector operable to generate an error signal that is related to a phase difference between a reference signal and a delayed output signal,
- a signal-controlled oscillator coupled to the phase detector and operable to generate on the output node an output signal having a frequency that is related to the error signal, and
- a feedback circuit coupled to the phase detector and to the oscillator and operable to generate the delayed output signal by delaying the output signal substantially by the signal delay.
4 more elements
An electronic system, comprising:
- an integrated circuit, comprising,
- a circuit,
- a delay path having an output node coupled to the circuit, an input node, and a signal delay, and
- a phase-locked loop having an output node coupled to the input node of the delay path, the phase-locked loop comprising,
- a phase detector operable to generate an error signal that is related to a phase difference between a reference signal and a delayed output signal,
- a signal-controlled oscillator coupled to the phase detector and operable to generate on the output node an output signal having a frequency that is related to the error signal, and
- a feedback circuit coupled to the phase detector and to the oscillator and operable to generate the delayed output signal by delaying the output signal substantially by the signal delay.
4 more elements
A method, comprising:
- generating an error signal that is related to a phase difference between a reference signal and a delayed output signal;
- generating an output signal having a frequency that is related to the error signal;
- and
- generating the delayed output signal by delaying the output signal substantially by a same time that the output signal is delayed along a path to a circuit that receives the output signal.
1 more element
A method, comprising:
- designing a circuit having a delay;
- and
- replicating the circuit in a feedback path of a phase-locked loop.
Dependencies are inferred from the claim text.