Method and circuit for synchronizing signals
AssigneeCheerteck, Inc.
InventorChia-Yow Yeh
Life of this patent
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Abstract
The invention relates to a method and circuit for synchronizing two signals triggered by clocks of different frequencies, which samples the lower frequency write-enable signal at both positive and negative edges of the higher frequency clock. If the sampling result at the positive or negative edge of the higher frequency clock is “1”, the state is recorded to be a “lock state” and no sampling is taken from the next opposite edge. If the sampling result at the positive or negative edge is “0”, the state is recorded to be a “sampling state” and the next opposite edge will be sampled. Finally, the sampling results taken at the positive and negative edges are joined to output a synchronized write-enable signal.
Claims10
A circuit for synchronizing two signals triggered by clocks of different frequencies, comprising:
- a recording circuit for recording sampling states of a higher frequency clock at a positive edge and a negative edge;
- and
- a sampling circuit for sampling a lower frequency write-enable signal at opposite edges of the positive edge and the negative edge according to the states, and joining sampling results respectively sampled from the positive edge and the negative edge to output a synchronized output signal.
A method for synchronizing two signals triggered by clocks of different frequencies, comprising the steps of:
- (a) initializing states at a positive edge and a negative edge of a higher frequency clock to be sampling states;
- (b) sampling from a lower frequency write-enable signal at the positive edge and the negative edge of the higher frequency clock, respectively, and recording states at the positive edge and the negative edge of the higher frequency clock;
- (c) sampling at a next opposite edge according to each state at the positive edge and the negative edge of the higher frequency clock,;
- and
- (d) joining sampling results of the lower frequency write-enable signal obtained respectively at the positive edge and the negative edge of the higher frequency clock, and outputting a synchronized write-enable signal.
If the sampling result from the lower frequency write-enable signal at the positive edge or the negative edge of the higher frequency clock is 1, the state at the positive edge or the negative edge is changed to be a lock state, or if the sampling result is 0, the state at the positive edge or the negative edge is changed to be a sampling state.
Dependencies are inferred from the claim text.