Input circuit, display device and information display apparatus
AssigneeCanon Kabushiki Kaisha
InventorsSomei Kawasaki, Fujio Kawano, Masami Iseki
Life of this patent
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AssigneeCanon Kabushiki Kaisha
InventorsSomei Kawasaki, Fujio Kawano, Masami Iseki
Estimating the term…
A first current mirror circuit (M2, M3 and M7) performs its normal operation when a first switch (M2) is turned on, and is constructed so that a period during which the first current mirror circuit can output a current is realized when the first switch is turned off. A second current mirror circuit (M4 and M9) is connected to the first current mirror circuit so that the output current of the first current mirror circuit is decreased by an output current of the second current mirror circuit. A current output of a transistor (MB) and a current output of the first current mirror circuit are connected and outputted as an output signal. The first switch (M2) and a second switch (M5) are controlled by the output signal or a signal formed by the output signal being passed through a buffer circuit.
An input circuit which receives first and second signals at its input and outputs an output signal having a level difference different from the first and second signals, comprising:
Dependencies are inferred from the claim text.